ISC Bit Setting for Interrupt Service Routine

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The discussion focuses on selecting the appropriate ISC bit setting for configuring an interrupt service routine. The user seeks to trigger an interrupt when an input signal on a pin goes high. The suggested setting is EICRA = (1<<ISC11), which corresponds to the rising edge of the interrupt. Participants emphasize the importance of knowing the specific processor being used for accurate configuration. Properly setting the ISC bits is crucial for effective interrupt handling in embedded systems.
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I'm setting up an interrupt service routine, but I'm unsure which ISC bit setting I should use.

ISC bit settings:

ISCx1 ISCx Description
0 0 Low level of INTx generates an interrupt request
0 1 Any logic change on INTx generates an interrupt request
1 0 The falling edge of INTx generates an interrupt request
1 1 The rising edge of INTx generates an interrupt request

I want the interrupt to take place, when an input signal on a pin in the external interrupt control register goes high.

Would the following ISC bit setting be correct:

EICRA = (1<<ISC11)
 
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It might help if you identified the processor you are using.
 
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