JFET Biasing in Cascode: Designing a High Input Impedance Differential Amp

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SUMMARY

The discussion focuses on designing a high input impedance differential amplifier using JFETs, specifically addressing the biasing of J1, the first JFET. The presence of a blue wire in the circuit was debated, as it affects DC offset and current flow through the bottom JFET. Removing the blue wire and adding a 100 K resistor from the gate to the bias resistor is recommended to eliminate DC offset while maintaining proper biasing. The use of high-value resistors is crucial for optimal performance in this configuration.

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SadScholar
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Hi, I'm trying to design a simple differential amp with extremely high input impedance. I'm using a couple of JFETs at the input stage to accomplish this. However, because I'm sending the signal from there to a differential amp, I don't want any DC offset, but I'm a little bit confused about how to bias J1, the first JFET. Basically my question is, should the blue wire be there. Even assuming I am dealing with two JFETs on the same silicon chip, and using the same value for both resistors, if I leave out that blue wire, I get a DC offset. But if I leave that blue wire in, I get almost no current through the bottom JFET and resistor, which is confusing to me. Any insight would be appreciated.
Here is the circuit diagram:
http://i516.photobucket.com/albums/u324/chrysolite13/CascodeCircuit.png
 
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SadScholar said:
Hi, I'm trying to design a simple differential amp with extremely high input impedance. I'm using a couple of JFETs at the input stage to accomplish this. However, because I'm sending the signal from there to a differential amp, I don't want any DC offset, but I'm a little bit confused about how to bias J1, the first JFET. Basically my question is, should the blue wire be there. Even assuming I am dealing with two JFETs on the same silicon chip, and using the same value for both resistors, if I leave out that blue wire, I get a DC offset. But if I leave that blue wire in, I get almost no current through the bottom JFET and resistor, which is confusing to me. Any insight would be appreciated.
Here is the circuit diagram:
http://i516.photobucket.com/albums/u324/chrysolite13/CascodeCircuit.png

Your blue wire would appear to short the input to the output, no?
 
Hah, that explains why it removes the offset.
 
There should be high value resistors from the gate to the bottom of the bias resistor for both FETS. So cut your blue wire and put a 100 K resistor in there.

But wouldn't you drive the bottom one and bypass the gate on the top one?

This would give more gain.
 
The attached is the schematic of TL081 JFET Opamp. Does that help?
 

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Most likely this can only be answered by an "old timer". I am making measurements on an uA709 op amp (metal can). I would like to calculate the frequency rolloff curves (I can measure them). I assume the compensation is via the miller effect. To do the calculations I would need to know the gain of the transistors and the effective resistance seen at the compensation terminals, not including the values I put there. Anyone know those values?

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