MOSFET Design Doubt: Explaining Positive Voltage

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Discussion Overview

The discussion revolves around the design of MOSFETs, specifically addressing the implications of connecting the substrate to the source terminal and the conditions under which the device operates. Participants explore the relationship between the drain and source voltages and how this affects the operation of NMOS and PMOS transistors.

Discussion Character

  • Technical explanation, Debate/contested

Main Points Raised

  • One participant seeks clarification on a statement regarding the connection of the substrate to the source and its effect on the pn junctions in MOSFET design.
  • Another participant asserts that the substrate and source are typically connected and that this connection does not cut off the transistor.
  • A question is raised about whether the discussion pertains to NMOS or PMOS devices.
  • It is noted that if the drain is at a positive voltage relative to the source, the device is likely an NMOS unless operated in inverse mode, which is uncommon.
  • One participant explains that with the substrate connected to the source, the back-to-back pn junctions create a non-conducting path for the drain-source, leading to the enhancement-mode MOSFET being in cut-off without gate voltage.

Areas of Agreement / Disagreement

Participants express differing views on the effect of connecting the substrate to the source, with some asserting it does not cut off the device while others suggest it can lead to a non-conducting state under certain conditions. The discussion remains unresolved regarding the implications of these connections.

Contextual Notes

There are assumptions about the operating conditions of NMOS and PMOS devices that are not fully explored, and the discussion does not clarify the specific scenarios under which the substrate connection affects the transistor operation.

shawrix
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Can someone explain this sentence in MOSFET design..

The Since the drain will be at a positive voltage relative to the source the two pn junctions can be effectively cut off simply connecting the substrate terminal to source terminal.
 
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As far as I know the substrate and source are usually connected, and does not cut off the transistor in any way.
 
Is it NMOS or PMOS?
 
shawrix said:
Can someone explain this sentence in MOSFET design..

The Since the drain will be at a positive voltage relative to the source the two pn junctions can be effectively cut off simply connecting the substrate terminal to source terminal.

Since the drain is stated to be more + than the source, the device is an NMOS unless the device is operated in the inverse mode, which is almost never the case.

As stated in a previous post, the souce & substrate are usually but not always connected. That connection does not cut off the device.
 
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shawrix said:
Can someone explain this sentence in MOSFET design..

The Since the drain will be at a positive voltage relative to the source the two pn junctions can be effectively cut off simply connecting the substrate terminal to source terminal.

... with the substrate connected to the source, the two back-to-back pn junctions cause the drain-source path to be a non-conducting path. Under these conditions (with the absence of gate voltage) the enhancement-mode MOSFET is in cut-off.
 

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