Engineering Negative PSRR of the Two-Stage Op Amp

Thread starter eyeweyew
Start date Feb 27, 2024
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Circuit analysis Cmos Ic design

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The discussion focuses on modeling the PSRR of a Two-Stage Op Amp as outlined in a specific lecture note. It highlights the differences in modeling when VBias is connected to ground versus Vss, particularly questioning the treatment of rds7 in both scenarios. Additionally, there is confusion regarding the exclusion of Cgd5 from the model, despite its negligible impact on the results. Understanding these modeling nuances is crucial for accurate PSRR analysis in op-amp design. The conversation emphasizes the importance of thorough comprehension of circuit elements in CMOS analog design.

Feb 27, 2024

eyeweyew

Homework Statement: Negative PSRR of the Two-Stage Op Amp with VBias Connected to ground vs connected to Vss

Relevant Equations: PSRR- model for Two-Stage Op Amp with VBias Connected to ground

From page 4-9 of this lecture note https://pallen.ece.gatech.edu/Academic/ECE_6412/Spring_2004/L180-PSRR-2UP.pdf, it gives example on how to model a Two-Stage Op Amp to find the PSRR- when V_Bias is connecting to ground as oppose to when V_Bias is connecting to V_ss. One thing I don't understand is why r_ds7 is modelled differently given that it is connecting V_out and V_ss in both cases?

Also, not sure why C_gd5 is not included in the model? although it doesn't make any difference to the outcome.

Reference:
CMOS analog circuit design. Authors: Phillip E. Allen, Douglas R. Holberg.
pg.307-309
[Link to full PDF copy of textbook redacted by the Mentors]

Last edited by a moderator: Feb 28, 2024