Engineering Negative PSRR of the Two-Stage Op Amp

AI Thread Summary
The discussion focuses on modeling the PSRR of a Two-Stage Op Amp as outlined in a specific lecture note. It highlights the differences in modeling when VBias is connected to ground versus Vss, particularly questioning the treatment of rds7 in both scenarios. Additionally, there is confusion regarding the exclusion of Cgd5 from the model, despite its negligible impact on the results. Understanding these modeling nuances is crucial for accurate PSRR analysis in op-amp design. The conversation emphasizes the importance of thorough comprehension of circuit elements in CMOS analog design.
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Homework Statement
Negative PSRR of the Two-Stage Op Amp with VBias Connected to ground vs connected to Vss
Relevant Equations
PSRR- model for Two-Stage Op Amp with VBias Connected to ground
From page 4-9 of this lecture note https://pallen.ece.gatech.edu/Academic/ECE_6412/Spring_2004/L180-PSRR-2UP.pdf, it gives example on how to model a Two-Stage Op Amp to find the PSRR- when VBias is connecting to ground as oppose to when VBias is connecting to Vss. One thing I don't understand is why rds7 is modelled differently given that it is connecting Vout and Vss in both cases?

Also, not sure why Cgd5 is not included in the model? although it doesn't make any difference to the outcome.

Reference:
CMOS analog circuit design. Authors: Phillip E. Allen, Douglas R. Holberg.
pg.307-309
[Link to full PDF copy of textbook redacted by the Mentors]
 
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