PMOS Working Concept: Vgs (th) -5V Source Follower Mode Output

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To operate a PMOS transistor in source follower mode, a negative gate-source voltage (Vgs) is required, typically around -5V. The discussion reveals that the gate and source are tied together at -5V, which allows for proper operation despite initial confusion about the voltage reference. A circuit diagram was requested to clarify the setup, and it was confirmed that a PMOS FET is being used. The key takeaway is that the configuration allows for output despite the negative Vgs, as the source voltage is effectively referenced to ground. Understanding the voltage relationships is crucial for successful PMOS operation.
hemant03
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Hi,
I believe that to make a PMOS work, Vgs (th) needs to be negative but when I give -5V to source and connect it in a source follower mode i.e. vg = -5V, I do get an output.
Can anyone tell me how and why?

Thanks,
- Hemant
 
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1. Can you post a circuit diagram.

2. Can you make it clear whether you are using mosfets or jfets.
 
Last edited:
uart said:
1. Can you post a circuit diagram.

2. Can you make it clear whether you are using mosfets or jfets.

Hi,
I have attached a sample PMOS circuitry that I have simulated. I am actually using a PMOS FET.
 

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Thats because you shorted the gate and the source together. They are tied to -5 Volts with respect to ground but not -5 volts with respect to source.
 

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