# Sparking through glass despite being below breakdown voltage

I'm anodically bonding a 0.5 mm silicon wafer to a 0.5 mm Pyrex 7740 glass wafer. My silicon wafer has a thick layer of oxide on its surface, and because it this insulating layer requires a high voltage to produce a strong bond.

The setup that I constructed is illustrated below (using 1800-2000V now rather than 900V), and consists of the two wafers sandwiched between two graphite plates that act as anode and cathode. The breakdown voltage for Pyrex 7740 glass is 13 MV/m, or 6500V for a 0.5 mm thick wafer. However, once the voltage gets to around 1800V, I begin to hear an electrical fizzing noise coming from inside the oven. When bonding is finished, I see hundreds of tiny pits all over the glass surface, the same as when you hit glass with an arc of electricity. This never happens at 900V, just at the higher voltages. Can someone explain why this might be happening? I'm not an electrical engineer, nor an expert on electronics by any stretch of the imagination.

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I will hazard a guess.
Voltage behaves as a pressure, and pressure = force/area. One way to think about it; a force tries to push things out of the way, a pressure tries to punch holes through things.
If the two surfaces are not in uniform contact, there could be tiny contact points where the (voltage) pressure will exceed the breakdown point.
I don’t know how you can solve that; maybe a heavier weight to hold the plates together?

tech99
Gold Member
I will hazard a guess.
Voltage behaves as a pressure, and pressure = force/area. One way to think about it; a force tries to push things out of the way, a pressure tries to punch holes through things.
If the two surfaces are not in uniform contact, there could be tiny contact points where the (voltage) pressure will exceed the breakdown point.
I don’t know how you can solve that; maybe a heavier weight to hold the plates together?
I'm anodically bonding a 0.5 mm silicon wafer to a 0.5 mm Pyrex 7740 glass wafer. My silicon wafer has a thick layer of oxide on its surface, and because it this insulating layer requires a high voltage to produce a strong bond.

The setup that I constructed is illustrated below (using 1800-2000V now rather than 900V), and consists of the two wafers sandwiched between two graphite plates that act as anode and cathode. The breakdown voltage for Pyrex 7740 glass is 13 MV/m, or 6500V for a 0.5 mm thick wafer. However, once the voltage gets to around 1800V, I begin to hear an electrical fizzing noise coming from inside the oven. When bonding is finished, I see hundreds of tiny pits all over the glass surface, the same as when you hit glass with an arc of electricity. This never happens at 900V, just at the higher voltages. Can someone explain why this might be happening? I'm not an electrical engineer, nor an expert on electronics by any stretch of the imagination.
Not an expert in the bonding process, but I understand electron tunneling can take place across oxide layers. It happens at voltages lower than the breakdown voltage. Could this perhaps be giving small conductive points where damage occurs? Maybe you could limit the current flow to a lower value by using a high resistance to prevent damage.

Baluncore
2019 Award
Is the pitting on the glass-graphite contact surface or on the glass-silicon bond zone.

I think it will come down to the accuracy of the surfaces and surface contamination. Is the oxide layer on the silicon flat ?
What might remain between surfaces during the bonding process ?

Is the pitting on the glass-graphite contact surface or on the glass-silicon bond zone?
I looked at it very carefully just now while using an aluminum cathode I use for bonding smaller pieces. The pitting is much worse when using aluminum vs. graphite and I can see the location of pits very clearly. They are indeed on the top of the glass, where glass meets cathode. My silicon wafer is prime grade and extremely flat, and I grow oxide in a tube furnace making it extremely flat as well. Before bonding, I do a piranha clean and drying in a cleanroom before putting the wafers in conformal contact. So it's very clean, but I always manage to get a few particles of dust between them.

Could this perhaps be giving small conductive points where damage occurs? Maybe you could limit the current flow to a lower value by using a high resistance to prevent damage
That's a good point. I chose high quality isomolded graphite to make the electrodes as uniform as possible, and I do the best I can to make it smooth using polishing papers from 15 down to 2 microns. I end up with a mirror finish on the graphite, however there could still be dust particles of graphite on the surface. Maybe these could act as conductive points. My power source is already at a very low current of 1 mA, so low in fact that when bonding pure silicon to glass the voltage drops to about 200V during the bonding process.

Voltage behaves as a pressure
I was reading something about electrostatic pressure decreasing as the oxide layer on silicon increases. I didn't think much of it at the time because I didn't really understand electrostatic pressure, but your analogy to the pressure I'm used to dealing with makes sense.

Just out of curiosity, how much contact force does the ss weight apply?
Some wafer bonding systems are able to apply 10-20 kN of contact force.

Baluncore
2019 Award
My power source is already at a very low current of 1 mA, so low in fact that when bonding pure silicon to glass the voltage drops to about 200V during the bonding process.
That suggests the glass has an average resistance of 200V / 1mA = 200k ohms. Is it really possible that high temperature lowers the resistance of the large area of bulk glass ?

Or could it be the average resistance with time of individual 500um long current filaments as they cause the pits ?

Maybe high voltage, HV, breakdown of the glass occurs, causes a pit which then heals, the supply voltage rises again, another breakdown occurs and causes the next pit. That does explain the fizzing sound. You could confirm the sequential pit formation by monitoring the bond voltage with a high voltage probe on an oscilloscope. An estimate of the number of voltage “dips” should correlate with the number of pits.

I would expect a fast voltage drop, then a period during which the voltage stays low while the pit forms and the supply capacitance discharges, followed by a slow rise back to the HV, until sufficient voltage is reached to initiate the next strike.

If the HV supply has a larger than necessary parallel output capacitance then it may be the energy stored in that capacitance that is making the pits. By isolating or limiting the HV capacitance and so reducing available energy, the spot welding may then not damage the surface of the glass.

What is unusual about your HV supply compared with the supplies used for bonding by others ?
Could the voltage breakdown of the glass be caused by ionising radiation, before or during bonding ?

Just out of curiosity, how much contact force does the ss weight apply?
With those kinds of forces, you're probably doing direct bonding with heat. I've worked on two commercial anodic bonders before, and they had a maximum of around 100 N, but in direct bonding mode this was significantly higher. In my system, I just apply about 15-20 N.

@Baluncore, you're right on the money in your prediction. When bonding pure silicon to glass, this is what I experience: 1) Voltage is cranked up, holds steady for 1-2 minutes 2) voltage starts to plummet, first very quickly to about 1/3 of its highest value, then a bit slower until it bottoms out between 150-250V 3) Voltage begins to climb at rate between 0.1V/s to about 1V/s until it reaches maximum again 4) once at maximum again, it's easy to adjust the voltage up and down.

However, I should clarify a few things. Even in the commercial systems, I still see the pitting at 900V. Actually, my setup with the graphite electrodes produces far less pitting than the commercial systems at the same voltage. The only difference in the power source that I know of is that mine puts out 1 mA while the commercial ones put out 10-20 mA. My friend in mechanical engineering built his own system off of my design (same components) but his power source puts out 10 mA and he never experienced a voltage drop.

The idea of current filaments is really interesting and I'd like to explore it further. As an environmental engineer, I don't have much access to electronics and no one I know of has an oscilloscope, but we do have a student workshop in MechSE that probably has one.

I'm not sure how to change the capacitance, or even measure it. Our power source is a good 20-25 years old, and just has one screw that you use to adjust the voltage from 0 to -15kV DC.

My friend in mechanical engineering built his own system off of my design (same components) but his power source puts out 10 mA and he never experienced a voltage drop.
Interesting. This begs the question though, does your friend's system exhibit the same amount of pitting?

Now that I don't know unfortunately. I just sent a text to the guy to ask him, and will post his reply if I receive one. We lost contact for about a year.