Understanding Capacitor Behavior in Clamper Circuits

[Princu]

I have having some serious doubts in clamper circuits.
For example,let me take the example of a +ve clamper circuit.

http://www.daenotes.com/images/positive-clamper.gif


The diode I am considering is an ideal one.In the notes,it is written that during the negative half cycle of the A.C input signal,diode becomes forward biased and it acts as a short circuit path and output across the load resistor will be zero.Fine.No problem upto this.

I am having trouble understanding the next sentence.
During this time,capacitor is charged to peak value of input voltage.My question is that if we apply Kirchoff voltage law in the circuit,then we will end up with the equation V(input)=V(capacitor) i.e. the voltage across the capacitor will be the same as the input.If that is the case,then won't the capacitor first charge(reach max voltage) in the first part of negative half cycle and then discharge(voltage zero) in the second part of the negative half cycle itself.This will inhibit the usage of the capacitor as a source of voltage as portryaed in the positive half cycle of circuit.But I know that what I am telling is not the case.Where I am thinking wrong? My lectures doesn't teach well and I am not able to grasp what she is saying.What do I do in this situation?

Please help me.I am totally confused.Thanks in advance.

 

[NascentOxygen]

The capacitance is large, it doesn't discharge much at all during one half-cycle. Once an equilibrium is established, you can regard the voltage across the capacitor itself as fixed and essentially constant.

It may prove informative to look at the posts listed at the foot of this page ⇓⇓