Basic question about RLC circuits

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Discussion Overview

The discussion revolves around the design and operation of an RLC circuit, specifically focusing on achieving resonant voltage across a capacitor at high frequencies. Participants explore the implications of component values, circuit configurations, and the relationship between impedance and applied voltage.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • One participant questions the feasibility of using a 0.1 nF capacitor at 100 MHz, suggesting that the capacitance value may be inappropriate for such a high frequency.
  • Another participant emphasizes the importance of knowing the resistance value in the circuit, as it directly affects the obtainable voltage across the capacitor.
  • A participant mentions the calculated resistance of the capacitor plates as 0.1 Ω and seeks clarification on whether other resistances should be considered.
  • Concerns are raised about the necessity of providing a circuit diagram to better understand the setup and resonance coupling.
  • Some participants suggest that the user may need to study reactive circuit elements further to clarify their questions and improve understanding.
  • One participant provides a calculation for the reactance of the capacitor at 100 MHz, indicating that to achieve 500 V across the capacitor, a significant current would be required.
  • Another participant discusses the design of a coaxial resonator as a potential solution for generating the required electric field for an ion trap, detailing its structure and function.
  • Participants express uncertainty about the optimal circuit configuration (series vs. parallel) and the implications of minimizing resistance to reduce the required applied voltage.

Areas of Agreement / Disagreement

Participants do not reach a consensus on the best approach to design the RLC circuit or the appropriateness of the component values. Multiple competing views and uncertainties remain regarding the circuit configuration and the implications of impedance on voltage requirements.

Contextual Notes

Participants reference specific calculations and theoretical concepts, but there are unresolved questions about the practical implications of component choices and circuit design. The discussion includes assumptions about ideal conditions that may not hold in practical applications.

Who May Find This Useful

This discussion may be useful for individuals interested in RLC circuit design, particularly in high-frequency applications, as well as those exploring the relationship between circuit components and resonance behavior.

  • #31
Malamala said:
Do you have an idea (or can you point me towards some readings) about how well a properly implemented feedback loop can keep the frequency of the setup stable (i.e. what changes in the resonant frequency should I expect in a given amount of time)?
The operating frequency of the resonator, would be as stable as the signal generator crystal, say 1:105, (which could be GPS locked if needed to 1:1012). The frequency would always be correct, only the phase could change, because the resonator is driven by the signal generator through the PA.

If the peak of the resonator moved away from the signal generator frequency, the resonator continues at the signal generator frequency. The thing that changes with the tuning of the resonator, is the amplitude of the resonance. For a low-Q resonator that is not a problem, but for a high-Q resonator it could significantly reduce the amplitude of the voltage. By measuring the resonator phase shift deviation, the PLL would pull the resonator back onto the reference frequency, restoring the amplitude, with zero phase error.

When the PA is loosely coupled to the resonator, there will be a phase shift across the resistive coupling network. That occurs because the reactance of the resonator is no longer zero at the operating frequency. The task of the PLL is to recognise a non-zero phase shift, and to pull the resonator back to zero reactance.
 
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  • #32
Baluncore said:
The operating frequency of the resonator, would be as stable as the signal generator crystal, say 1:105, (which could be GPS locked if needed to 1:1012). The frequency would always be correct, only the phase could change, because the resonator is driven by the signal generator through the PA.

If the peak of the resonator moved away from the signal generator frequency, the resonator continues at the signal generator frequency. The thing that changes with the tuning of the resonator, is the amplitude of the resonance. For a low-Q resonator that is not a problem, but for a high-Q resonator it could significantly reduce the amplitude of the voltage. By measuring the resonator phase shift deviation, the PLL would pull the resonator back onto the reference frequency, restoring the amplitude, with zero phase error.

When the PA is loosely coupled to the resonator, there will be a phase shift across the resistive coupling network. That occurs because the reactance of the resonator is no longer zero at the operating frequency. The task of the PLL is to recognise a non-zero phase shift, and to pull the resonator back to zero reactance.
I am sorry for the confusion. What I meant to ask is how much does the resonant frequency of the resonator circuit is expected to change (for a well done feedback loop)? Of course the actual frequency will be the driving one, but I would like to know how much should I expect the Q-factor at that driving frequency to change. For reference, I need the amplitude of the electric field in between the parallel plates to be as stable as possible, thus I need the change in the difference between the resonant frequency of the circuit and the driving frequency to be minimized (and this difference should ideally be zero).

For example, for a PDH lock of a laser to a cavity, you can lock the laser frequency to 1/1000 of the cavity linewidth. I am looking for a similar estimate here, when locking the circuit itself to the fixed driving frequency. Basically, for a driving frequency of 35 MHz, should I expect a variation of the circuit resonant frequency (under the feedback loop) on the order of tens of kHz? Can I go lower than that?
 
  • #33
Malamala said:
What I meant to ask is how much does the resonant frequency of the resonator circuit is expected to change (for a well done feedback loop)?
The physical stability of the resonator's self-resonant-frequency, is decided by materials, construction, and environment.

The aim is to operate the resonator on the flat top of the Q curve. A PLL is able to bring the self-resonant-frequency, to the driven operating frequency, and to lock it there. By monitoring the PLL output voltage, you can confirm that the resonator has been phase locked to the drive signal.

Malamala said:
Of course the actual frequency will be the driving one, but I would like to know how much should I expect the Q-factor at that driving frequency to change.
To minimise the variation in Q, over the range of PLL regulated operation, identify if it is the inductor or the capacitor that is most significant in causing the deviation. Then use the PLL output to correct that component.
 

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