Understanding CPU L3 Cache: Intel Core i3-2130 Specs and How It Works

[biferi]

I have an intel core i3-2130 CPU and I ran the CPU-Z program to get the specs on it.

It told me my L3 Cache was 3MB and my L2 was 256kB.

Now for my L1 it gives it into lines like this
L1 Data 32kB
L1 Instructions 32kB.

Now I would gess that my L1 is Divided into 2 Blocks of 32kB Chunks.
And the Block that says Data 32kB means this is where it works on Data.

And the Block that says Instructions 32kB this is where it store Instructions for Devices>

Am I right?

Thank you for all your time.

 

[phyzguy]

Everything looks right except where you say "instructions for devices". I'm not sure what you mean by "devices". The instruction cache is where it stores the program statements for whatever the CPU is doing at the moment. No matter what the CPU is doing, it is taking some type of data and operating on the data according to some stored instructions. These data and instructions are what are stored in the L1 caches. The L2 and L3 caches are "unified" caches, meaning they can be storing a mixture of data and instructions, but the L1 cache is divided into separate data and instruction caches. Does this help?

 

[biferi]

Thanks a lot it did help me but one more thing?

If my L1 Cache is 32kB does this mean my CPU is not a 64 Bit CPU?

Because it only can do work on 32kB of Data at a time?

 

[phyzguy]

No, it means the cache is 32 kilobytes. Since it's a 64 bit word, that means it consists of 512 64 bit words. As it works through these 512 64 bit words, it is continually bringing in new data from the L2 cache.

 

[rcgldr]

No, it means the cache is 32 kilobytes. Since it's a 64 bit word, that means it consists of 512 64 bit words. As it works through these 512 64 bit words, it is continually bringing in new data from the L2 cache.

I would think that even the L1 cache "line" size is larger than 8 bytes, probably 16 bytes or more.

 

[biferi]

Well if a CPU is a 64 Bit Processor I thought it means it Processes 64 Bits at a time.

So if my L1 Cache is 32kB and it is working on 32kB at a time then it is a 32 Bit CPU.

But you say NO it is just working through the Data at 32kB Chunks.

But this is what makes me think it is a 32kB CPU a 64 Bit CPU would work on 64 Bits at a time right?

 

[phyzguy]

So if my L1 Cache is 32kB and it is working on 32kB at a time then it is a 32 Bit CPU.

How do you conclude this? Are you clear that 32 kB means 32,768 bytes, each of which is 8 bits? This means it can hold 4096 64 bit words (I said 512 earlier - this was a mistake). The CPU isn't working on all of this at once. This is just what is stored in the L1 cache. The CPU is still processing data 64 bits at a time regardless of how big the L1 caches are. I don't understand where you are confused.

 

[SteamKing]

You know, you can download all sorts of specs on CPUs from the Intel website:

http://www.intel.com/content/www/us/en/processors/core/core-i3-processor.html

This is just for the Core i3 processors.

 

[Routaran]

So if my L1 Cache is 32kB and it is working on 32kB at a time then it is a 32 Bit CPU.

I believe you are thinking there is a connection between the number '32' in 32 kiloByte L1 cache and a 32 bit processor. There is not.

Your L1 cache holds a max of 32 kiloBytes of data. It doesn't really have anything to do with processor architecture.

The conversion, as phyzguy pointed out:
1 kilo = 1024
1 Byte = 8 bits
So,
32 kB = 32kB * (1024/k) * (8bits/B) = 262144 bits

Since we're dealing with a 64 bit processor: (each piece of data or each "word" is 64 bits long)
the L1 cache can hold:
262144bits / (64bits/word) = 4096 words, each of which is 64 bits in length

This is simply the max amount of data that can stored in the L1 cache. The amount of L1 cache is not a direct indication of the processor architecture. (Well you kind of/sort of can but it's really splitting hairs so let's not do that, stick with general principles so we can talk sensibly about the big picture)

For example, the 486 processor, the P5 and P6 processors were all 32 bit processors but each had a different amount of L1 cache.
The 80486 used 8kB of L1 cache (65536 bits or 2048 "words", each 32 bits in length)
The P5 used 16kB of L1 cache (131072 bits or 4096 "words", each 32 bits in length)
The P6 used 32kB of L1 cache (262144 bits or 8192 "words", each 32 bits in length)
L1 cache size was different but in each case, the processor worked with data that was 32 bits in length.

 

[rcgldr]

Keep in mind that in addition to the 32kb L1 cache size for data, an array of most of a 32 bit or 48 bit (if in 64 bit mode) virtual address is also stored in the L1 cache, one virtual address per line of cache. It's unlikely to have a L1 cache where each line only holds 4 or 8 bytes of data, since the address storage overhead would be excessive. There's also the memory width size to consider; 16 bytes for dual channel, 24 bytes for tripple channel, and 32 bytes for quadruple channel.

 

[biferi]

I think I know what I am not getting.

L1 is just how many Bits it can work on at a time and it is a storage place.

I think I am mixing Cache with Registers.

CPUs have Exturnal and Inturnal Registers.

And the Exturnal Register is how many Bits it can take in at one time and also how much Memory it can see.

Am I right?

 

[Mark44]

I think I know what I am not getting.

L1 is just how many Bits it can work on at a time and it is a storage place.

The caches are storage units of a certain size that are organized into "cache lines". Access by the CPU to the cache is faster than to ordinary memory in RAM, but not as fast as the access to the registers.

I think I am mixing Cache with Registers.

CPUs have Exturnal and Inturnal Registers.

No. The registers are internal. On the Intel CPUs there are the general purpose registers, such as AX, BX, CX, and DX (16-bit CPUs such as 8088), EAX, EBX, ECX, and EDX (32-bit CPUs such as 80386), RAX, RBX, RCX, RDX (64-bit CPUs such as P6). There are a few more general purpose registers that I didn't list. There are also registers to keep track of the current instruction (IP, EIP, or RIP), and the current stack location (SP, ESP, RSP), and the flags register, and segment registers. There are no external registers.

And the Exturnal Register is how many Bits it can take in at one time and also how much Memory it can see.

Am I right?

Like you said, you are confusing caches with registers.

 

[SteamKing]

An even more basic confusion on the part of the OP is that the sizes of the cache have nothing to do with the number of bits which can be handled by the registers.

And the length of the registers used for calculation may not necessarily have the same length as the address registers. For example, early CPUs like the intel 8080 had 8-bit general purpose registers but used 16-bit address registers.