Understanding D Flip Flop Behavior: Clock Effects on NAND Gates

[Jakes]

when D will be 0 then in the first input to the lower nand gate will be 1 and the first input to the upper nand gate will be 0 If clock (CLK) = 1 then in the upper Nand gate 0 NAND 1 will be 1
and in the lower nand gate 1 NAND 1 will be 0.
now In the Second upper NAND gate 1 will go as the first input and the second input will be Q Complement ... Now what will be this Q complement or Q' 0 or 1 .. and Why ??

 

[NascentOxygen]

If you know ANY input on a NAND gate is logic 0, then you know the output of that gate must be 1, regardless of any other of its other inputs.

That property comes from the truth table for NAND gates.

 

[rcgldr]

When CLK == 1, then the left upper NAND gate will output ~D and the left lower NAND gate will output D. Then the upper right NAND gate will output D to Q and the lower right NAND gate will output ~D to Q'. So when CLK == 1, Q == D, and Q' = ~D

After this, if CLK == 0, Q and Q' will not change regardless of D.

Note, if the initial state is CLK == 0, and Q == Q', then a race condition exists.