1. Limited time only! Sign up for a free 30min personal tutor trial with Chegg Tutors
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Timing Diagrams for D Flip-Flops

  1. Feb 21, 2015 #1

    Zondrina

    User Avatar
    Homework Helper

    1. The problem statement, all variables and given/known data

    Complete the timing diagram for the following circuit:

    Screen Shot 2015-02-21 at 10.35.46 AM.png

    2. Relevant equations


    3. The attempt at a solution

    So I was doing some pre-midterm studying, and I was slightly confused with the operation of this circuit.

    I think part of the solution provided is incorrect, but I'm not positive so I thought I would ask. Here is my attempt so far at filling in the waveforms:

    Screen Shot 2015-02-21 at 9.58.09 AM.png

    I believe the value of ##B## provided at that clock edge is incorrect (the place where I have not connected the lines).

    At that rising clock edge, the rising edge triggered D flip-flops will start by copying the value of ##\bar x## into ##A##. Hence why ##A = 1## at that clock edge.

    Then looking at the NOR gate before the second D flip-flop, the inputs should be ##A = 1## and ##x = 0##. This results in ##0##. Should this not imply that ##B = 0## and not ##B = 1## as they have provided?

    EDIT: I also forgot to ask, does synchronous reset have any impact on a rising edge triggered D flip-flop for a falling clock edge? I have ignored the reset in the early portions of the waveform because it was a falling clock edge.
     
    Last edited: Feb 21, 2015
  2. jcsd
  3. Feb 21, 2015 #2

    Zondrina

    User Avatar
    Homework Helper

    Wait wait, I think I see how I was reading the diagram incorrectly before. Would this be the answer:

    Screen Shot 2015-02-21 at 11.01.16 AM.png
     
  4. Feb 21, 2015 #3
    These are positive edge-triggered?

    To me it looks like B should be low at all times, since either x or A is high on CLK. C should then be high after first CLK until reset, since x AND B is never true.
     
  5. Feb 21, 2015 #4

    Zondrina

    User Avatar
    Homework Helper

    Yes, these are rising edge triggered (probably master-slave d-latch) D flip-flops. So when the CLK is high, the master is transparent and the slave is latched.

    I also thought ##B## should be low at all times at first, but they provide part of the solution, and ##B## goes high at one point. This changed the way I interpreted the diagram.

    If ##B## really does go high at the point they have indicated, then the only way that could happen is if they are sampling the values of the input variables ##x## and ##A## just before the rising clock edge.

    So for the point where ##B## goes high in the solution they provided, I read it like so:

    ##x = 0## before the rising edge.
    ##A = 0## before the rising edge.

    ##0## NOR ##0## is ##1##, therefore ##B = 1## just after the rising edge.

    I think this is because of the operation of the actual D flip-flop itself. They way it sends the values through just after the clock goes high, but it samples them a very small instant just before the clock goes high.

    Therefore, I believe the image in post #2 is correct.
     
    Last edited: Feb 21, 2015
  6. Feb 21, 2015 #5

    CWatters

    User Avatar
    Science Advisor
    Homework Helper

    I agree with the wave form for B in post #2.

    The data on D is sampled on the rising edge of the clock only. The data must be valid for a short time (Tsetup) before the rising edge and held for a short time after the rising edge (Thold). Apart from that changes to D at any other time do not effect Q.

    So looking at the second latch...

    Just prior to the first rising edge of clk... X = 0 and A = 0. So the data input to the latch will be 1. That means after the rising edge B = 1.
    Just prior to the next rising edge of clk .. X = 0 but A = 1. So the data input to the latch will be 0. That means after the rising edge B = 0.
    etc
     
  7. Feb 21, 2015 #6

    CWatters

    User Avatar
    Science Advisor
    Homework Helper

    PS Normally the output of a latch will take time to change after the clock edge. This delay plus the NOR gate delay helps ensure that Thold is met for the next latch in the chain.
     
  8. Feb 22, 2015 #7
    I took the view that the flip-flops were transparent on positive-edge CLK, but that doesn't make any sense, since they then wouldn't function as delay elements. Apologies.
     
  9. Feb 22, 2015 #8

    CWatters

    User Avatar
    Science Advisor
    Homework Helper

    An example would be the 7474.
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted



Similar Discussions: Timing Diagrams for D Flip-Flops
Loading...