Need Explanation of this Master Slave D Flip Flop

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Discussion Overview

The discussion revolves around the necessity of specific connections in a master-slave D flip-flop circuit, particularly regarding preset and clear functionalities. Participants explore the implications of these connections on the circuit's behavior and memory elements.

Discussion Character

  • Technical explanation
  • Conceptual clarification
  • Debate/contested

Main Points Raised

  • One participant questions the necessity of certain highlighted wires in the circuit diagram, wondering if connections at the last stages of NAND gates are sufficient.
  • Another participant explains that both pairs of U5+U6 and U7+U8 form memory elements, suggesting that presetting or clearing must affect both to maintain circuit integrity.
  • A later reply reiterates the importance of addressing both memory elements to prevent the circuit from reverting to previous states after releasing preset or clear actions.
  • One participant asserts that connections mentioned are essential for achieving a specific output when the slave is active, indicating a requirement for the circuit's operation.

Areas of Agreement / Disagreement

Participants express differing views on the necessity of the highlighted connections, with some supporting their importance while others question their role. The discussion remains unresolved regarding the sufficiency of the existing connections.

Contextual Notes

Participants do not fully explore the implications of their claims, and there may be missing assumptions regarding the behavior of the flip-flop under different conditions.

u_know_who
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Please look @ the pictures below. I have drawn a master slave D flipflop with preset and clear option as mentioned in the book.

http://i28.lulzimg.com/7e22bfc016.png

Can anyone tell me what is the necessity of the wires that are highlighted in the image? isn't the wire @ last stages of NAND gates enough?
 
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The pairs of U5+U6 and U7+U8 both form memory elements. So if you really want to preset or clear the entire circuit you most do that action on both memory elements. If you only did it to U7+U8 then you could force the desired output, but as soon as you release the preset or clear the circuit would just revert back to whatever was stored in U5+U6.
 
Floid said:
The pairs of U5+U6 and U7+U8 both form memory elements. So if you really want to preset or clear the entire circuit you most do that action on both memory elements. If you only did it to U7+U8 then you could force the desired output, but as soon as you release the preset or clear the circuit would just revert back to whatever was stored in U5+U6.

Hmm, i think that's the answer of my question. Thank you. :)
 
Well after studied what i have found that it is a must. You can't set ouput 0 by pressing clear = 0 when the slave is active (clock = 0) unless u give those connection that i mentioned.
 

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