1. The problem statement, all variables and given/known data A D flip-flop is implemented using an S-R master-slave flip-flop that changes states on the falling edge of the clock. Assume that the circuit is fabricated using NAND gates and that each gate has exactly a propagation delay Tpd = 1ns. a) Determine the set-up (Tsu), hold (Th), and propagation delay (Tpd) parameters for this D flip-flop. b) *Convert a master-slave S-R flip-slop into a J-K using the appropriate gates. *Compare the behaviour of this circuit to a falling edge-triggered J-K flip-flop. What are the fundamental differences? 2. Relevant equations N/A 3. The attempt at a solution I watched this video ( ) and, it helped me somewhat understand the basics but, I am still not too certain as to what is going on, specifically, and I'm unsure as to how I should start this problem. I don't know what else to say but, if you need to me to say something, ask me. Any help in solving this problem would be greatly appreciated!