D flip-flop, S-R master-slave flip-flop, falling edge of clock, NAND

[s3a]

Homework Statement

A D flip-flop is implemented using an S-R master-slave flip-flop that changes states on the falling edge of the clock. Assume that the circuit is fabricated using NAND gates and that each gate has exactly a propagation delay Tpd = 1ns.

a) Determine the set-up (Tsu), hold (Th), and propagation delay (Tpd) parameters for this D flip-flop.

b)
*Convert a master-slave S-R flip-slop into a J-K using the appropriate gates.
*Compare the behaviour of this circuit to a falling edge-triggered J-K flip-flop. What are the fundamental differences?

Homework Equations

N/A

The Attempt at a Solution

I watched this video ( ) and, it helped me somewhat understand the basics but, I am still not too certain as to what is going on, specifically, and I'm unsure as to how I should start this problem.

I don't know what else to say but, if you need to me to say something, ask me.

Any help in solving this problem would be greatly appreciated!

 

[CWatters]

Draw the logic diagram for the D-Type using NAND gates. Explore what happens when you keep the clock = 1 but D changes. The change on D will propagate around inside the latch. What happens if the clock falls while that's still happening? Will the output Q end up as the old or new value of D? If you want Q to become the new value of D how long do you need to allow for the change to propagate around inside the latch before the clock can change. That's the set up time.