Using propagation delays to my advantage?

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The discussion centers on using a 555 timer and 7400 series logic devices to manage the timing of a D flip-flop based on propagation delays. The design aims to ensure that the 555 timer output stabilizes before a clock signal is detected by the flip-flop, leveraging the inherent delays in the logic gates. Concerns are raised about the effectiveness of this approach, as propagation delays can vary and may require circuit adjustments. Suggestions include reviewing datasheets for precise timing and considering alternative methods to achieve the desired timing without relying solely on propagation delays. Overall, while the concept is feasible, careful consideration and testing are necessary to ensure reliable operation.
vsage
Hello,

I am currently using a 555 timer to check the period of a square wave input: The timer is triggered off the leading edge of the first square pulse, and if a second leading edge is detected OR the 555 becomes untriggered then a clock signal will be sent to a D flip flop and its state will change to the value of the output of the 555 timer at the instant the clock changes.

In my design (all 7400 series logic devices btw) I tie the 555 timer output directly to the D of the D flip flop, and the clock is two logic gates away from the 555 timer output but is ultimately controlled by it. In this way, I hope to rely on the fact that there is a propagation delay through the logic gates so that the 555 timer has been high for a little bit of time before a leading clock edge is detected at the clock of the D flip flop.

I stopped short of looking at a schematic of the D flip flop and the logic gates I am using (just AND and OR ones), but is it sound to assume my design would work based on propagation time? I am also open to suggestions on maybe some more classic ways of doing what I am trying to do as stated in my first paragraph. Also, the period of the square wave input is only in the ms range.
 
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Not really sure what you are doing. How are you triggering the D flip-flop. Are you timing the D flip-flop with a separate reference clock?

If I remember correctly, the propagation delay of the 7400 series is like 20 to 60 nanoseconds per gate. If you are working with milliseconds, the even the rise time won't be that fast.
 
It is possible to use propogation delays to make sure logic levels are set before clocking occurs but I can't see what you are trying to achieve or how the circuit achieves based on your description.
Can you give a state diagram?
What ever the solution propogation delays are not an exact science so you will probably need to tweak the circuit. When using propogation delays you need to have all the data sheets for every chip in order to work out the analogue waveform rather than the digital states. If of course you just want a fixed delay stick it through every stage of an inverter chip.
In the dim and distant past I have built oscillators and random number sources based on chip propogation delays so it is feasible to use them to your advantage.
 
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