Voltage drop across drain-source for stacked MOSFETs

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Discussion Overview

The discussion revolves around the voltage drop across stacked MOSFETs in a circuit, focusing on the conditions under which the MOSFETs operate, particularly in saturation and linear modes. Participants explore the implications of threshold voltages and the behavior of the devices under different bias conditions.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • One participant notes that Vs1, Vs2, and Vs3 cannot exceed 4.3 V to ensure the MOSFETs turn on, questioning whether the voltage drop of 0.7 V accumulates across the devices.
  • Another participant asks why all three gate voltages are equal, suggesting confusion over how different operating modes can exist under the same bias conditions.
  • A participant emphasizes that if R is much greater than Rds(on), the current flow can be simplified, and clarifies terminology regarding Vtn and Vgs(th), asserting that the latter is more commonly used in the field.
  • There is a discussion about the conditions under which an N-MOSFET turns on, with some participants asserting that it can conduct even when Vds is negative if Vgs is above the threshold voltage.
  • One participant expresses difficulty in determining the voltage drops across the MOSFETs when they are in saturation mode, comparing it to the behavior of silicon diodes.
  • Another participant clarifies that the behavior of MOSFETs in saturation differs from that of silicon diodes, stating that a MOSFET acts like a resistor in saturation.

Areas of Agreement / Disagreement

Participants express differing views on the behavior of MOSFETs under various conditions, particularly regarding the accumulation of voltage drops and the implications of operating modes. There is no consensus on how to approach the voltage drop calculations across the stacked MOSFETs.

Contextual Notes

Participants highlight limitations in their understanding of the circuit's behavior, particularly regarding the assumptions made about the operating conditions of the MOSFETs and the definitions used for threshold voltages.

jaus tail
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Homework Statement
When three n type mosfets are stacked, what will be potential across V(ds)3 where:
DS1 is drain source of 1st mosfet. Drain is connected to Vdd. Source is connected to drain of second mosfet. Source of second mosfet is connected to third mosfet. Source of third mosfet is connected to resistance that is grounded

Vdd --> Vd1s1 --> Vd2s2 --> Vd3s3 --> R --> Ground
Relevant Equations
Mosfet turns on when Vgs > Vtn and Vds > (Vgs - Vtn)
Here's the circuut:
1659082487572.png

Vtn is 0.7 V. So Vs1 (wrt ground) cannot be more than 4.3 V else M1 won't turn on.
Likewise Vs2 and Vs3 (wrt ground) cannot be more than 4.3 V else M2 won't turn on.
So Vs3 = 4.3 V. Even voltage across final resistance is 4.3 V
Assume there's no drop across Mosfet.

But I'm not sure. Will the drop of 0.7 be accumulated. Like Vs3 would be Vdd - 3 times Vtn?
Will Vs3 (wrt ground) be 4.3 V or (5-3 times 0.7) = 2.9 V

The 2 scenarios for this question are:
1) All mosfets are in saturation mode
2) The mosfets can be in linear mode
 
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Why are all 3 gate voltages equal in this scenario?
jaus tail said:
The 2 scenarios for this question are:
1) All mosfets are in saturation mode
2) The mosfets can be in linear mode
How can you have different situations with the same bias condition?
 
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First, let's assume R >> Rds(on). Rds(on) is the device resistance (drain to source) when it's saturated. This means we don't have to worry about resistive dividers and how much current is flowing.

Second, what you are calling Vtn everyone else calls Vgs(th) (the Gate Source Threshold Voltage). OK, it's somewhat arbitrary what you call things. But... EVERYONE who works with MOSFETs uses Vgs(th), get used to it. Also be suspicious of people who choose a different name, they probably haven't read many MOSFET datasheets, which means they haven't worked in this field much.

OK, now...

Mosfet turns on when Vgs > Vtn ---- Yes.

Mosfet turns on when Vds > (Vgs - Vtn) ---- No. N-MOSFETS can be on even when Vds < 0. This isn't just the built in body diode. They can conduct in either polarity through the channel if Vgs > Vgs(th). This is commonly used in synchronous rectifier circuits to reduce losses since the voltage drop across the channel is (usually) lower than the voltage across the body diode.

Each N-MOSFET is on if Vgs > Vgs(th), it's really that simple. When the MOSFET is on, the drain is essentially connected to the source with a channel resistance of Rds(on), a small value in this case.

So, you have a set of rules (one, really) about when a MOSFET is on. This seems pretty easy to apply in this circuit. Maybe you can think about this and explain again about what is confusing you?
 
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DaveE said:
Mosfet turns on when Vgs > Vtn ---- Yes.

Mosfet turns on when Vds > (Vgs - Vtn) ---- No. N-MOSFETS can be on even when Vds < 0. This isn't just the built in body diode. They can conduct in either polarity through the channel if Vgs > Vgs(th). This is commonly used in synchronous rectifier circuits to reduce losses since the voltage drop across the channel is (usually) lower than the voltage across the body diode.

Each N-MOSFET is on if Vgs > Vgs(th), it's really that simple. When the MOSFET is on, the drain is essentially connected to the source with a channel resistance of Rds(on), a small value in this case.

So, you have a set of rules (one, really) about when a MOSFET is on. This seems pretty easy to apply in this circuit. Maybe you can think about this and explain again about what is confusing you?
Ok.. So if Vgs(th) > 0 and if Vds < 0, then also the Mosfet is On, however current direction is reversed. Makes sense.

But assuming that Vgs(th) >0 and all Mosfets are in saturation mode with current flowing from drain to source,
I'm not able to figure out the drop across M1, M2, and M3

The voltage Vd2(wrt ground) and Vd3(wrt ground).

In case of Si Diodes, we take voltage drop as 0.7 and keep on subtracting in series.
Is that the same case here?
berkeman said:
Why are all 3 gate voltages equal in this scenario?

How can you have different situations with the same bias condition?
No, the situations are different. The gate voltages are just sufficient enough to turn on the mosfet as in. Vgs > threshold voltage.

I have no idea how this circuit will work. Electrical engineering is easy with RLC but electronics makes it difficult when diodes and fets come in.
 
jaus tail said:
In case of Si Diodes, we take voltage drop as 0.7 and keep on subtracting in series.
Is that the same case here?
No, not for NMOS. A MOSFET in saturation acts just like a resistor.
 
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