What are the Vgd and Vgs of the Load NMOS in This NMOS Loaded NMOS Inverter?

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Discussion Overview

The discussion revolves around determining the gate-to-drain voltage (Vgd) and gate-to-source voltage (Vgs) of the load NMOS in an NMOS loaded NMOS inverter circuit. Participants explore the implications of various input voltages (Vi) and the operational modes of the transistors involved, focusing on theoretical calculations and simulation results.

Discussion Character

  • Homework-related
  • Technical explanation
  • Exploratory
  • Debate/contested

Main Points Raised

  • One participant states that the NMOS load is always in linear mode and provides an equation for the drain current (Id).
  • Another participant questions the meaning of the parameters (W/L)o and (W/L)L, seeking clarification on their roles in the circuit.
  • Some participants clarify that (W/L)o refers to the lower transistor and (W/L)L refers to the upper transistor (load).
  • There is a discussion about the variable nature of Vi, with some suggesting it could range from 0V to 5V, while others express concern about the implications of this range on the operational modes of the transistors.
  • A participant mentions that if Vi varies from 0 to 5V, it could complicate the analysis, suggesting the use of simulation software like PSpice.
  • Simulation results are shared, indicating values for Voh, Vol, and Vm, prompting questions about their theoretical accuracy.
  • Another participant proposes a method for computing voltages based on different assumptions about the operational modes of the transistors.
  • There is a request for clarification on the Vgs of the O transistor, considering the presence of a Vgg tied to it.
  • One participant suggests using an Excel spreadsheet for calculations, indicating a preference for organized data analysis.

Areas of Agreement / Disagreement

Participants express varying views on the operational modes of the transistors and the implications of different input voltages. There is no consensus on the exact values of Vgd and Vgs, and the discussion remains unresolved regarding the theoretical versus simulated results.

Contextual Notes

Participants note that the load FET may not always be in linear mode, especially when Vi is at certain values. There are also unresolved assumptions regarding the operational modes of the transistors based on the input voltage.

InuyashaITB
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Homework Statement


NMOS%20inverter_zpshjemzera.png

Given
Vdd = 5v, Vgg = 10v, Kn' = 20uA/V^2 (For both transistors), (W/L)o = 10um/5um, (W/L)L = 5um/20um, Vt = 1.1V (for both)

My question is what would be the Vgd, and Vgs of the load NMOS?

Homework Equations


upload_2015-9-19_12-50-11.png

The Attempt at a Solution


So far, what i have is:
The NMOS Load is always in linear mode. Id = Kn[(Vgsl – Vt)Vdsl – 0.5*Vdsl^2]

Vi = Vgso

Vo = Vdso
 
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(W/L)o = 10um/5um, (W/L)L = 5um/20um
What are these?

Kn' = 20uA/V^2
Why Kn'? why the prime?

 
The W/L is the width over the length of the channel of the transistors. Basically Kn = Kn'*W/L
 
rude man said:
(W/L)o = 10um/5um, (W/L)L = 5um/20um
which is which? does "o" stand for the upper and "L" for the lower transistor?
also need to know Vi.
 
The O is the lower transistor, the L is the upper transistor (L for Load)
 
InuyashaITB said:
The O is the lower transistor, the L is the upper transistor (L for Load)
Vi?
 
Vi would be variable, from 0 to Vdd
 
The original question to this problem is to re-create its VTC curve and find all of the critical points of the VTC (Vm, Voh, Vol, Vih, Vil, NMh, NML, and power dissipation
 
InuyashaITB said:
Vi would be variable, from 0 to Vdd
It can vary all the way from 0V to 5V? That would make the problem a tall order. Do you have pspice? :smile:

Or maybe Vi is either 0V or 5V? That we could live with ...
 
  • #10
rude man said:
It can vary all the way from 0V to 5V? That would make the problem a tall order. Do you have pspice? :smile:

Or maybe Vi is either 0V or 5V? That we could live with ...

Yes, if we look at the extremes it would help
 
  • #11
InuyashaITB said:
Yes, if we look at the extremes it would help
OK. Because if you allow the entire range from 0 to 5V one or both devices will transition from one mode to another, making for a headache unless you do it with some kind of software. You could use spice or write your own high-level-language program.
Also, your statement that the load FET is always in the linear mode is incorrect sice there is effectively nothing connected to its source if Vi = 0.
Stay tuned.
 
  • #12
I simulated the circuit exactly as described
https://goo.gl/photos/bHLqKvAJKTMKLym86

It seems Voh=5v
Vol=1v
Vm = 2.5v

This is all according to simulation, would this be close to what the theoretical should be
 
  • #13
I will try to do a computation for Vi = 5V and 1V, maybe 2.5V also. Later.
EDIT: instead I will give you suggestions on how to proceed:
1. You have the L fet always in the linear mode, as you say.
2. assume the o fet is also in the linear mode. Equate the two fets' equations since the current is the same. Solve for all voltages. If the voltages meet the requirements for the linear mode for the o fet, you're done.
3. if not, then assume the o fet is in the saturated mode and repeat solving for all the voltages the same way.
For Vi = +2.5V and +5V the o fet has to be in either the linear or saturated mode.
For Vi = +1V it should be obvious what the mode of the o fet is.
Your simulation looks about right.
Remember you have Vd1 = Vs2 etc. The only unknown is Vd1 = Vs2.
P.S. an excel spreadsheet might be a good way to do this.
 
Last edited:
  • #14
rude man said:
I will try to do a computation for Vi = 5V and 1V, maybe 2.5V also. Later.
EDIT: instead I will give you suggestions on how to proceed:
1. You have the L fet always in the linear mode, as you say.
2. assume the o fet is also in the linear mode. Equate the two fets' equations since the current is the same. Solve for all voltages. If the voltages meet the requirements for the linear mode for the o fet, you're done.
3. if not, then assume the o fet is in the saturated mode and repeat solving for all the voltages the same way.
For Vi = +2.5V and +5V the o fet has to be in either the linear or saturated mode.
For Vi = +1V it should be obvious what the mode of the o fet is.
Your simulation looks about right.
Remember you have Vd1 = Vs2 etc. The only unknown is Vd1 = Vs2.
P.S. an excel spreadsheet might be a good way to do this.
So what would be the Vgs of the O transistor seeing as how there is a Vgg tied to the O transistor
 
  • #15
rude man said:
I will ty to do a computation for Vi = 5V and 1V, maybe 2.5V also. Later.
InuyashaITB said:
So what would be the Vgs of the O transistor seeing as how there is a Vgg tied to the O transistor
 
  • #16
InuyashaITB said:
So what would be the Vgs of the O transistor seeing as how there is a Vgg tied to the O transistor
You mean QL, not "the O transistor", right? To avoid further confusion, I am using the subscript "1" for Qo and "2" for QL henceforth:
You have every voltage except Vd1 which is also Vs2:
Vg1 = Vi (i.e. 1V, 2.5V and/or 5v)
Vg2 = +10V
Vd2 = +5V
Vs1 = 0
So, solve for Vd1 which is also Vs2.
 

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