Question in small signal model for NMOS

In summary, this conversation discusses the design of a common source circuit with source resistance using the MOSFET (irfp244). The small signal output gain is set to be around 5 by choosing appropriate values for R1 and R2, with the assumption that 1/gm is much less than R2. The value of ID is calculated using the equations Id = (1/2) KN (VGS - Vt)2 and Id = Vsource / R2. The plot of Vout and Vin is examined for different input voltages, and it is explained that the small signal gain collapses as the input is increased due to the cut-off of the MOSFET. The process of choosing R1 and R2 for
  • #1
a.hambouth
1
0

Homework Statement


Design the following circuit, common source with source resistance, in fig. (1). It uses the MOSFET (irfp244) where Vt= 4.15V, KN = Kn(W/L)= 2.87 A/V2. Assume vin = +/- 100 mV, DC offset = 5 V, and the frequency = 1 K Hz.
a) Design R1 and R2 so that the small signal output gain, Av, is ~ 5. Assume 1/gm << R2.
b) What is the value of ID?
c) Plot Vout & Vin when vin = +/- 400 mV, +/- 700 mV, and +/- 1V separately.
d) Explain why the small signal gain collapses as the input is increased.

Homework Equations


Id = (1/2) KN (VGS - Vt)2
Id = Vsource / R2 , Id = (10-Vout) / R1 , Av = Vo/Vin = R1 /((1/gm)+R2)

The Attempt at a Solution


Now what I did I assumed that from Av = R1/R2 =5 that R1=250ohm and R2=50ohm I found from Id = (1/2) KN (VGS - Vt)2 & Id = Vsource / R2 that Vs = 0.96599V or Vs = 0.74794V the first Vs is not accepted because the N-MOSFET will be off (Vgs > Vt) and the second will be on ( VG-Vg swing - Vs > Vt) . and the value for Id will be 14.9588 mA . but the problem is changing the Vin ! because the mosfet will be cut off from (Vg - Vg swing - Vs < Vt) but the multisim still give me value for Vout and Vin for different Av , Can anyone tell me what i did wrong ?
 

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  • #2
EDIT: Oops, you're OK for zero input volts (in addition to the 5V bias of course)!

Your equations are all good. The given input offset voltage is only 5V which isn't much above Vt for this device.

But, OK. If you go with R2 = 50 ohms then your Vs and i are correct. But, when Vin = 4.9V I got i = 0.013A with Vs = 0.013*50 = 0.65V. The device is not cut off at 4.9V input. I suggest you made a math boo-boo when putting Vin = +4.90V.

Of course, as you drop Vin below 4.9V it eventually will cut off.

P.S. You could have gone to smaller R2, then R1 still = 5R2 of course and the current levels could have been much higher, as intended by this power transistor.
 
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  • #3
is there a way to find R1 and R2 other than assumption ?
 
  • #4
mrxxdragonxx said:
is there a way to find R1 and R2 other than assumption ?

You choose R1 and R2 to give you the power level and voltage gain you want. Two requirements, two resistors to select.

Usually though one of them is given (like a heater load or whatever).
 
  • #5

Your approach to finding the values for R1 and R2 is correct. However, in order to plot Vo and Vin for different values of Vin, you need to use the small signal model for the NMOS transistor. This model includes a small signal voltage source (Vgs) and a small signal current source (Id). These sources represent the changes in the gate-source voltage and drain current due to the small signal input (Vin).

To plot Vo and Vin for different values of Vin, you will need to use a simulator or hand calculations to solve for the small signal output voltage (Vo) and small signal input voltage (Vgs) at each value of Vin. You can then plot these values on a graph to see how they change as Vin increases.

As for the collapse of the small signal gain as Vin increases, this is due to the saturation region of the transistor. As Vin increases, the transistor will eventually enter into the saturation region where the drain current (Id) is independent of the gate-source voltage (Vgs). This results in a decrease in the small signal gain.
 

1. What is the small signal model for NMOS?

The small signal model for NMOS is a simplified representation of the behavior of an NMOS (n-channel metal-oxide-semiconductor) transistor in its active region. It is used to analyze the response of the transistor to small changes in input signals.

2. Why is the small signal model important?

The small signal model allows for easier analysis of the transistor's behavior in response to small changes in input signals. It is particularly useful for designing and optimizing circuits that use NMOS transistors.

3. What are the key components of the small signal model for NMOS?

The key components of the small signal model for NMOS include the transconductance parameter (gm), output resistance (ro), and input capacitance (Cgs). These parameters represent the transistor's gain, output impedance, and input impedance, respectively.

4. How is the small signal model different from the large signal model?

The small signal model is a linearized version of the large signal model, which means it only considers small changes in input signals and assumes the transistor is operating in its active region. The large signal model, on the other hand, takes into account all possible operating conditions of the transistor.

5. How is the small signal model used in circuit design?

The small signal model is often used in conjunction with other circuit analysis techniques, such as Kirchhoff's laws and Ohm's law, to design and optimize transistor-based circuits. It allows for easy calculation of the transistor's gain and input/output impedances, which are important factors in circuit performance.

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