What happens when the switch is closed in a 555 timer and left there?

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SUMMARY

The discussion focuses on the behavior of a 555 timer when the trigger switch is closed during the timing cycle. It highlights that the timer triggers on the negative-going edge of the input pulse and requires the trigger voltage to exceed one-third of the supply voltage for proper timing. If the trigger remains low longer than the timing cycle, the output remains high, regardless of the threshold comparator state. Additionally, variations in 555 timer behavior among different manufacturers are noted, emphasizing the importance of using the correct chip for specific configurations.

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  • Research the specific trigger requirements of the 555 timer from the Phillips datasheet
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Solarmew
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Here's my circuit
pic1.JPG


The question at hand is what happens when the trigger switch is closed during the timing cycle (after being closed once already to initiate said cycle)

here's the waveform I'm getting, but I'm not sure what to make of it.
pic2.JPG


could someone please help me understand what it's doing?
 
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is it because the capacitor doesn't have time to charge, so when it tries to trip, it's forced to go back immediately?
 


10K X 100 uf = 1 second time constant.
You're showing a pulse every 14 microseconds.

I'd guess C1 is more like 100 picofarads.
Have you a photo of it, or is this a simulation?

Try bypassing the supply with a few uf physically near the 555... that's always good practice because 555 takes a gulp of current when it switches.

old jim
 


this is just a simulation, i didn't get a chance to do this on a breadboard because we ran out of time :< but i wanted to see what happens if i do it in MultiSim ... and this is what happens (see pic of the waveform) ... and i have no idea why
 


From the Phillips datasheet available here,
http://www.doctronics.co.uk/pdf_files/555an.pdf

Trigger Requirements
Due to the nature of the trigger circuitry, the timer will trigger on the
negative-going edge of the input pulse. For the device to time-out
properly, it is necessary that the trigger voltage level be returned to
some voltage greater than one third of the supply before the timeout
period. This can be achieved by making either the trigger pulse
sufficiently short or by AC coupling into the trigger. By AC coupling
the trigger (see Figure 3), a short negative-going pulse is achieved
when the trigger signal goes to ground. AC coupling is most
frequently used in conjunction with a switch or a signal that goes to
ground which initiates the timing cycle. Should the trigger be held
low, without AC coupling, for a longer duration than the timing cycle
the output will remain in a high state for the duration of the low
trigger signal, without regard to the threshold comparator state.
This
is due to the predominance of Q15 on the base of Q16, controlling
the state of the bistable flip-flop. When the trigger signal then returns
to a high level, the output will fall immediately. Thus, the output
signal will follow the trigger signal in this case.

I don't trust that simulation.

old jim
 
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I haven't scrutinized the operation in question here. But I can point out that not all 555's are the same. For input combinations outside those encountered in the timer's myriad designed applications, chips from different manufacturers can and do behave consistently differently.

So for configurations outside the norm, you may find yourself confined to using a particular manufacturer's 555 to provide the i/p o/p characteristic you want.
 
Most likely this can only be answered by an "old timer". I am making measurements on an uA709 op amp (metal can). I would like to calculate the frequency rolloff curves (I can measure them). I assume the compensation is via the miller effect. To do the calculations I would need to know the gain of the transistors and the effective resistance seen at the compensation terminals, not including the values I put there. Anyone know those values?

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