555 timer, 50% duty cycle astable, run from 5V

[Borek]

Follow up - after finding out it was capacitor that was source of the problems in the standard astable configuration, I have revisited the original "50%" circuit I tried at the very beginning. Using better capacitors didn't help, frequency was still highly dependent on the voltage and the duty cycle was never 50% (for R2=6.8 kΩ and C=40 nF I got 1826 Hz/63.0% @ 5 V and 2435 Hz/51.2% @ 15 V, 1 kΩ load on the output).

Just in case someone finds the first post and wonders if the idea is worth anything. Seems like it is not.

 

[Matt Hall]

Sorry to be so late to this particular discussion but I only just saw it whilst searching for 555 circuits.
I think it worthwhile adding my contribution as no-one has suggested my solution and someone in the future may find it handy.

The reason it's usually impossible to get a 1:1 mark:space ratio from a 555 is that the capacitor is being charged via the two resistors in series but only discharged via one of them. There are various solutions involving using diodes and / or transistors but all those have the unwanted side-effect of causing the frequency to vary with supply voltage.

My solution is very simple and needs just one component. All that is required is to change the threshold voltages for pins 2 and 6 of the 555. In astable mode the timing capacitor on pins 2 & 6 of the chip charges to the upper threshold (pin 6) and is then discharged to the lower one (pin 2) which starts the next cycle.
Those thresholds are set by a chain of 3 equal resistors (nominally 5kΩ) within the 555 chip. The upper threshold is 2/3 Vcc and the lower one half that.
As the upper threshold is exposed at pin 5 it can easily be manipulated using a resistor. Pulling it lower shortens the 'output high' part of the waveform without changing the 'output low' part.

In my experiment I used equal resistors for R1 and R2 (10k). With equal resistors pin 5 needs to be pulled down from 2/3 Vcc to about 4/9 Vcc (~0.44 Vcc) in order to equalise the high and low parts of the waveform. To achieve this a value of around 7k2Ω is needed for Rv.

The 555s internal resistors are well matched but may not be precisely 5kΩ so I suggest using a variable resistor for Rv so that an exact 1:1 ratio can be set.
The resulting waveform is very stable with regard to frequency and mark:space ratio when the supply voltage is altered.

Please note that the CMOS 555 chips have much larger values for their internal resistors so, although this technique should still work, a much larger value of Rv will be necessary.

The above circuit is not intended to produce the 2700Hz requested by the OP but could do so with the timing capacitor or resistors changed (e.g. 100n and 2k7).

 

[Tom.G]

For CMOS 555 timers, there is one that claims 50% duty cycle by connecting the cap to the divider chain with pins 2&5 2&6[/color] (TRIGGER & CONTROL) tied together and the timing resistor fed from pin 3 (OUTPUT). I haven't tried it, but seems like it would also work with bipolar logic (TTL).

see pg.4 of http://www.aldinc.com/pdf/ALD555.pdf

Cheers,
Tom

 

[Baluncore]

I haven't tried it, but seems like it would also work with bipolar logic (TTL).

Yes it works well with CMOS but needs a pull up resistor with the TTL version.
When input pins 2 and 6 are tied, without other components, the 555 is an inverting schmitt trigger with thresholds of 1/3 and 2/3 of Vcc.

 

[Tom.G]

Yes it works well with CMOS but needs a pull up resistor with the TTL version.
When input pins 2 and 6 are tied, without other components

That pointed out a pin number typo in my post regarding pin 5 vs. pin 6. (corrected now)

Where is the pull up resistor connected when using the TTL version?

 

[Baluncore]

Where is the pull up resistor connected when using the TTL version?

Between pin 3 output and V+ rail. Note that pin 7 can be an independent open collector output in that mode.
TTL outputs sink current from inputs. That means TTL output voltages do not need to go to the positive rail. Check the output voltage swing to select the PU resistor value.

 

[jim hardy]

For CMOS 555 timers, there is one that claims 50% duty cycle by connecting the cap to the divider chain with pins 2&5 (TRIGGER & CONTROL) tied together and the timing resistor fed from pin 3 (OUTPUT). I haven't tried it,

i've used that
it would be perfect if the output pulled pin 3 pull all the way to V+ and V-
but since there's headroom required that depends on load current
you have slight asymmetry in the charge and discharge paths.

TTL outputs sink current from inputs. That means TTL output voltages do not need to go to the positive rail. Check the output voltage swing to select the PU resistor value.

Yes !
IIRC the 555 has totem-pole output so it can sink or source 100 ma of current
http://www.ti.com/lit/ds/symlink/lm555.pdf

(EDIT - Well, as i said. 200 ma)
and you'd think output could drive to either rail

but it sinks better than it can source
it can source only to about a volt below positive rail in high state
but it'll sink almost to negative rail in low state

hence the asymmetry

a nice detail to be aware of...

old jim

 

[Matt Hall]

Old Jim is entirely correct. The output of the normal 555 never goes to the supply rails. That introduces errors which will not only result in asymmetry of the output waveform but will make the timings both supply voltage and load dependent. The CMOS version may be better in this respect, depending on the load.

The method of changing the thresholds which I described does not have those disadvantages. The output waveform barely changes with either supply voltage or load and symmetry can easily be achieved by tweaking the thresholds using the resistor from pin 5 to ground.

There are some minor disadvantages of my method. The 555 always has an inherent error in the length of the discharge phase (output low) caused by the small collector - emitter voltage of the discharge transistor (pin 7) and that gives a slight change in the timing of the output low phase with supply voltage. With reduced thresholds the effect of that error will increase somewhat. Likewise, the amount of jitter in the waveform timing will increase - a larger capacitor on pin 5 will help to keep that down.

If these disadvantages are a concern the best policy would be to have the 'charge' resistor (R1) much less than the 'discharge' resistor (R2) so that the thresholds need only be reduced slightly to achieve a 50:50 timing.

I have not seen the method I described in a manufacturer's data sheet (I certainly haven't read them all!) but a Signetics sheet from 1972 does show how to modulate the output high period by applying modulation to pin 5.

Matt

 

[jim hardy]

but a Signetics sheet from 1972 does show how to modulate the output high period by applying modulation to pin 5.

those old Signetics books are a treasure

see https://archive.org/details/bitsavers_signeticsdcsLinearVol1_11470058

table of contents

if you have room for a 100 meg document you'll love it. I just saved a copy to my PF folder.