What is the $@ symbol for in a makefile?

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In summary, The purpose of $@ in the dependency line is to represent the target of a rule, which in this case is the executable being created. This allows for more efficient and concise writing of makefiles. The make manual provides further information on this and other automatic variables.
  • #1
jf22901
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1
Hi.

Can anyone please tell me what purpose $@ serves in the dependency line below? I've tried looking online, and in the make and ifort documentation, but can't find anything. :confused:

Code:
$(EXECUTABLE) : $(OBJECTS)
                ifort $(LOADFLAGS) -o $@ $(OBJECTS) $(LIBRARIES)

where:

OBJECTS = list of object files
LOADFLAGS = -O3 -align dcommons
LIBRARIES = -L$(LIBRARY) -lfft -lnetcdf

Many thanks. :smile:
 
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  • #3

1. What does the $@ symbol represent in a makefile?

The $@ symbol in a makefile represents the name of the target file being generated.

2. How is the $@ symbol used in a makefile?

The $@ symbol is typically used in makefile recipes to denote the target file. It can also be used in variable assignments to define the target file as the value.

3. Can the $@ symbol be used in combination with other symbols in a makefile?

Yes, the $@ symbol can be used in combination with other symbols such as $< (representing the first prerequisite), $? (representing all the prerequisites that are newer than the target), and $^ (representing all the prerequisites).

4. How is the $@ symbol different from other symbols in a makefile?

The $@ symbol is unique in that it represents the target file specifically, while other symbols in a makefile may represent different aspects of the target or prerequisites.

5. Are there any limitations to using the $@ symbol in a makefile?

Yes, the $@ symbol can only be used in recipes or variable assignments. It cannot be used in other parts of a makefile, such as dependency lines or target names.

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