Why Are My Half-Adder Outputs Always Zero?

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I have an issue with the outputs from a half-adder. I am using three CD4007UBE chips and the outputs always stay at zero. I simulated using a model for the CD4007, and it worked without any issues. However, the actual circuit's outputs remain zero for every input.

The input signals are A and B. Each is connected to a separate function generator with a 5V square wave (5V high, 0V low). I have adjusted the frequencies and no matter what, the outputs are always zero. I noticed if I disconnect the wire connecting PIN 1 from x1 and PIN 5 from x2, the output C works.

I heard from some that it's not possible to use only three chips for this, since I have four NAND gates and an inverter (18 total transistors). I don't see why it would not work with three, if this is the case.

The circuit diagram is attached, as well as the model I'm using for the CD4007UB.

Any help is greatly appreciated.

EDIT: I modified the circuit and used four chips instead of three. Now, the C output is working correctly, but S is not. The S output is inverting whatever C is (so they're opposite) for some reason. Schematic is attached.
 
Attachments
  • LTspice schematic with three subcircuit blocks X1, X2 and X3 for CD4007 chips, voltage sources V1 to V3 and VDD, and PULSE sources labelled A and B.
    img1.jpg
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  • Schematic of three CD4007 CMOS chips wired as inverters and transmission-type stages, with pins labeled VDD (14), VSS (7), and nodes 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, plus SPICE model lines for P4007 and N4007 PMOS and NMOS devices.
    img2.jpg
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  • LTspice schematic with three voltage sources (VDD, A, B) and four CD4007 subcircuit blocks X1 to X4, with pin labels and a .tran 400u directive.
    img3.jpg
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I've spent some time looking over your post and attachments, but so far I'm not able to help much.

Could you please post schematics of what you are trying to do with those 4007 ICs? It would be best if you could post the logic schematic first, and then how you are trying to use those totem-pole CMOS transistor ICs to implement the logic schematic.

And there are pin definitions missing on your attachments. There are no ground connections, and no external connections for the totem pole component CMOS transistors. A more complete definition of what you are doing would help us to help you.
 
The logic diagram is attached. I made the four NAND gates using four 4007s and then the inverter uses the first 4007 (pins 9, 10, 11, 12). Someone else made the circuit using five NAND gates and they have the same issue (S output is the inverted C output).

I also found a top view of the 4007 with what each pin is (attached).

EDIT: If I disconnect the supply voltage (VDD), both outputs work correctly.
 
Attachments
  • Logic circuit diagram of a half adder built from NAND gates, with inputs A and B, outputs S = A XOR B and C = AB, and an inverter driving C.
    logic_ha.jpg
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  • Pinout diagram of a CD4007 dual complementary pair and inverter chip in a 14-pin DIP package, top view, with pin numbers and labels: Drain 2Dp, Source 2Sp, Input 2A, Source 2Sn, Drain 2Dn, Input 1A, VSS, Drain 1Dn, Source 3Sn, Input 3A, Source 3Sp, Output 3Y, Drain 1Dp, VDD.
    CD4007.png
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I managed to get the half adder working, but I used the xor transmission gate. I still have no idea why the xor using four nand gates did not work.
 
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When you are faced with ICs that you are unfamiliar with, you should first test individual gates by monitoring input and output as you apply various test inputs. Only when you are satisfied they are working and you understand them, should you connect multiple gates into something more complex.

It sounds like you didn't have the power supply correctly connected, or switched on, or something.
 
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I did all that, but still no go. It's odd that I wasn't the only one that could not get the design for the xor using 4 nand gates working (was a lab). They had the same problems.
 
hogrampage said:
I did all that, but still no go. It's odd that I wasn't the only one that could not get the design for the xor using 4 nand gates working (was a lab). They had the same problems.
Okay, here's a face-saving explanation which allows everyone to walk away from the situation with dignity intact: the lab had a batch of logic chips that inside the package were wired to the wrong pins. :wink: