Why is NGSPICE giving me wrong results for my inverter simulation?

  • Thread starter Thread starter Kholdstare
  • Start date Start date
Click For Summary

Discussion Overview

The discussion revolves around issues encountered while simulating a basic inverter circuit using the NGSPICE software with a specific MOSIS IBM 65nm model. Participants are exploring the discrepancies in delay results and potential causes for the unexpected output.

Discussion Character

  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant reports a significant discrepancy in delay times for their inverter simulation, expecting 8-15 ps but receiving 4 ns instead.
  • Another participant notes the presence of high capacitive Miller coupling effects in the simulation results.
  • A suggestion is made to adjust the transistor dimensions from default values (L=5um, W=5um) to more realistic values for the simulation.
  • A later post claims to have identified a bug in the simulation setup, although the specifics of the bug are not detailed.
  • One participant recommends using the NGSPICE website for running SPICE simulations, mentioning that it includes example circuits that could assist in troubleshooting similar issues.

Areas of Agreement / Disagreement

Participants do not reach a consensus on the cause of the discrepancies, as multiple potential issues are raised without resolution. The discussion remains open to further exploration of the problem.

Contextual Notes

The discussion does not clarify the specific assumptions or parameters used in the simulation that might affect the results. The impact of the suggested changes to transistor dimensions is also not explored in detail.

Kholdstare
Messages
388
Reaction score
1
I was trying to simulate basic inverter with mosis IBM 65nm model file (lvl 54 BSIM 4.3.0). And I am getting a delay of 4ns whereas I should get 8-15 ps. I don't understand why it is giving me wrong results. I suspect ngspice (ver 24) is doing it wrong.

Thnx

subckt.txt
* Inverter
.SUBCKT INV IN OUT
M1 OUT IN GND GND nmos
M2 OUT IN VDD VDD pmos
.ENDS

test.txt
* Inverter

.INCLUDE D:\ngspice\bin\0_Models_mosis_ibm_65nm_l54.ftr
.INCLUDE D:\ngspice\bin\subckt.txt
.GLOBAL GND VDD

XINV IN OUT INV
VDD VDD GND 1V
VIN IN GND PWL(0 0 10ns 0 10.1ns 1 30ns 1 30.1ns 0)

.TRAN 0.01ns 50ns
.END

.CONTROL
run
plot in out
.ENDC
 
Engineering news on Phys.org
Bump. I even see high capacitive Miller coupling effect.
 
Thnx,

your current circuit has transistors with L=5um and W=5um (default values). You may consider changing these to real values.

Holger
 
Yeah, found the bug at last.
 
For simple netlists like this, http://www.ngspice.com can be very helpful. This site allows you to run SPICE simulations from a web browser. There is also an example circuit similar to yours that may have helped to identify the problem that you were having.
 

Similar threads

Why does the CMOS inverter operate in triode mode in static operation?
  • · Replies 2 ·
Replies
2
Views
5K