- #1
mr_coffee
- 1,629
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Hello everyone, I'm confused on what they want me to do here:
it says:
Find a minimum gate input count realization of the enabling logic using AND and OR gates and inverters. Well This is my truth table i came up with, and the "enabler" is the M, the master switch( 0 secruit system on, 1 secuirty system off). Here is the picture: http://img145.imageshack.us/img145/6249/lastscan0oh.jpg any help would be great.
it says:
Find a minimum gate input count realization of the enabling logic using AND and OR gates and inverters. Well This is my truth table i came up with, and the "enabler" is the M, the master switch( 0 secruit system on, 1 secuirty system off). Here is the picture: http://img145.imageshack.us/img145/6249/lastscan0oh.jpg any help would be great.
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