- #1
sphyics
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Hi all,
Ckt diagram for ntype JFET
The values are as follows
V2 = -10 V , V1 = +10V
R1 = 1M ohm
R2 = 10 k ohm
IDss (drain current with shorted gate condition [tex]^{}_{}Vgs[/tex]= 10mA
Vp = 4v {Vp= pinch off voltage}
To find drain voltage Vd =?
http://img233.imageshack.us/img233/4007/19716664vu3.png
https://www.physicsforums.com/newattachment.php?do=manageattach&p=1600867
///////// SOLVED //////
For gate source loop
Vgg = V2 = -10 V
Vdd = V1 = +10V
From kirchhoffs law
(-Vgg ) – (Ig)* (Rg) – Vgs = 0 since (Ig ~= 0)
Vgs = (-Vgg) ------------------------------------------------------- ***********
By Shockley’s equation
Id = Idss( 1-(Vgs /Vp)^2
Id = 22.5 mA
For drain source loop
Vdd – (Id)*(Rd) – Vds = 0
Vds = Vdd – (Id)*(Rd)
Getting an absurd answer for Vds (= -215V)
aim was to obtain Vds then Vds = Vd – Vs; as Vs = 0, Vds = Vd
Can anyone help me out by pointing my fault in analysis. Or is there any other method to solve for Vd .
Ckt diagram for ntype JFET
The values are as follows
V2 = -10 V , V1 = +10V
R1 = 1M ohm
R2 = 10 k ohm
IDss (drain current with shorted gate condition [tex]^{}_{}Vgs[/tex]= 10mA
Vp = 4v {Vp= pinch off voltage}
To find drain voltage Vd =?
http://img233.imageshack.us/img233/4007/19716664vu3.png
https://www.physicsforums.com/newattachment.php?do=manageattach&p=1600867
///////// SOLVED //////
For gate source loop
Vgg = V2 = -10 V
Vdd = V1 = +10V
From kirchhoffs law
(-Vgg ) – (Ig)* (Rg) – Vgs = 0 since (Ig ~= 0)
Vgs = (-Vgg) ------------------------------------------------------- ***********
By Shockley’s equation
Id = Idss( 1-(Vgs /Vp)^2
Id = 22.5 mA
For drain source loop
Vdd – (Id)*(Rd) – Vds = 0
Vds = Vdd – (Id)*(Rd)
Getting an absurd answer for Vds (= -215V)
aim was to obtain Vds then Vds = Vd – Vs; as Vs = 0, Vds = Vd
Can anyone help me out by pointing my fault in analysis. Or is there any other method to solve for Vd .
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