|Jan4-12, 04:51 PM||#1|
CMOS inverter DC analysis
I have a question about how to analyze the CMOS inverter (this circuit: http://www.cs.umass.edu/~weems/CmpSc...e2/image10.gif). Just to clarify, the input voltage is connected to both gates, and the PMOS on top has its source connected to Vdd. The NMOS on the bottom has its source connected to GND. The drains of both FETs are connected, and it is at this node which we take our output to be.
Assume for now the transistors are matched such that V_tn = |V_tp| = V_t (equal threshold voltages), and k_n*(W/L)n = k_p*(W/L)p. Also say Vdd is 5v. In this example I'll be considering static operation (V_i is set to some value for all time).
So here's me trying to reason out what may happen. I know the answer, I just don't see why I don't exactly get there. Start with V_i = 0 (input voltage). This turns off the NMOS as V_gs = 0, no current flows in this transistor. Now we for the PMOS we know V_sg = Vdd > V_t so we can have either triode or saturation mode. What I can't properly reason through is why we must have triode mode in static operation. Comparing V_sd to V_ov I can see either case being possible.
V_sd = Vdd - V_o
V_ov = V_sg - V_t = Vdd - V_i - V_t = Vdd - V_t (since V_i = 0)
All I really know here is that Vdd is 5v, and V_t is, say, 1v. As I said before, I know the answer is supposed to be that the PMOS takes on triode mode. But I'm having trouble seeing what is wrong with saturation mode. Assuming V_sd > V_ov, this condition for saturation can still be valid. Working through the inequality, I get:
V_o < V_t (= 1v say.)
But clearly this does not give a logic high. Assuming triode mode (V_sd < V_ov) gives me the condition V_o > V_t, and my textbook furthermore replaces the PMOS with a small resistor with the value V_sd/I_d (which can be described purely in terms of device parameters, if V_sd is assumed so small that V_sd^2 can be neglected). Then the circuit just becomes Vdd connected to a resistor connected to the output node V_o. So then they conclude V_o = Vdd.
Any insights into why the circuit must operate in triode as opposed to saturation? Thanks.
|Jan4-12, 06:48 PM||#2|
As you stated the P is turned on but because it is in DC, and it has no load, then Vs=Vd=Vdd as Id=0A. Therefore Vov=Vsg-Vt=(5-0)-1 > Vsd=0, thus the P is in triode.
|Jan4-12, 06:54 PM||#3|
thanks for the reply es1.
So because the PMOS is on but not connected to any load we must have V_o = Vdd. I guess for the case of a parasitic capacitance from V_o to ground this doesn't affect the DC analysis either, thus keeping it in triode mode.
I think I get it, thanks again.
|cmos, inverter, saturation, transistor, triode|
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