...what is the effect for both suppose to be simultaneously or independently?A D flip flop is a type of sequential logic circuit that stores and outputs a single bit of data. It consists of a data input, a clock input, and two outputs - Q and Q̅. When the clock input signal transitions from low to high, the value of the D input is transferred to the output Q. This means that the output only changes when the clock signal changes, making it a synchronous device.
The main difference between a D flip flop and other types of flip flops, such as the SR flip flop or JK flip flop, is that it only has a single input - the D input. This makes it simpler to use and understand, but also means that it is limited in its capabilities.
In most cases, the set and reset inputs of a D flip flop are not asynchronous. This means that they will only take effect when the clock input is high, just like the D input. However, there are some designs of D flip flops that have asynchronous set and reset inputs, but these are less common.
Asynchronous set and reset inputs can be useful in certain applications where the timing of the set and reset signals is critical. For example, in a circuit that is designed to trigger an alarm when a certain condition is met, an asynchronous reset input can be used to immediately reset the circuit when the condition is no longer met.
In most cases, a D flip flop cannot be used as a direct replacement for an SR flip flop or JK flip flop. This is because it lacks the ability to set and reset the output independently, which is necessary in certain applications. However, in some cases, a D flip flop can be used in combination with other logic gates to simulate the functionality of an SR or JK flip flop.