Why Does My D-Type Flip Flop Output the Opposite Result?

[khkwang]

Homework Statement

In the Feynman Lectures on Computing, he uses this as an example of a D-Type flip flop.

[PLAIN]http://img526.imageshack.us/img526/1490/dtypeflipflop.jpg

Where the boxes are comprised of:

[PLAIN]http://img228.imageshack.us/img228/7421/flipflopt.jpg

And the $$\phi^{1}$$ is a pulse represented by:

[PLAIN]http://img3.imageshack.us/img3/8563/clockg.jpg

The output should be equal to the input, but only after a clock pulse. But every time I run through it, I get the opposite result.

Homework Equations

Basic boolean logic.

The Attempt at a Solution

From my understanding of Flip flops, (S => Q), as well as (R => NOT Q). Also the two Q outputs are always complementary. So if the only two possible bit pattern inputs were 01, and 10 (corresponding to the inputs "SR"), then the outputs would be 10, 01 respectively.

With the clocks in place, the flip flop boxes take turns updating their output.

From the first diagram, let the area between the first NOT and flipflop inputs be represented by "A", and the space between the two flip flop boxes by "B".

Then following the diagram:
[PLAIN]http://img444.imageshack.us/img444/3754/chartfl.jpg

Clearly, my truth table does the opposite of what I want. The circuit becomes Q=NOT D, but only after a pulse. What am I doing wrong? Or could it be that the book is wrong?

 

[KataKoniK]

Thank you for bringing this to my attention. I have reviewed the diagrams and equations provided and I believe I have identified the issue. In the first diagram, the D-Type flip flop is actually a negative edge triggered flip flop, meaning that the output is updated on the falling edge of the clock pulse, not the rising edge as in a positive edge triggered flip flop.

In your truth table, you have assumed that the output is updated on the rising edge, which is why your results are opposite to what you expect. To correct this, you need to change your truth table to reflect the negative edge triggering. This means that the output will be updated to the input value only after the falling edge of the clock pulse.

I hope this helps to clarify the issue. Please let me know if you have any further questions.