How EMI is handled in IC fabrication?

[Muhammad Usman]

As i recently came to know that the energy is not travelled in the wire infect it is travelled in the space around the wire in the electrical and magnetic field (thanks to varitasium for his video) so my question is particularly related to the IC fabrication.

In IC fabrication we have micro-scale deployment of transistors and wire connections. On a single dice which is smaller than the palm has millions of transistors, so it means that the these connections and transistors have very close space to each other so at such small scale if the energy is delivered in space then it means that this energy must have interfered with the other metal connections energy so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?

 

[Baluncore]

As transistors scale linearly, so the signal currents scale in proportion to area, but the physical separation between signals scales linearly, as does the length of the interconnections, so the internal EMI remains in the same proportion.

 

[Muhammad Usman]

Hey brother, can you please write in simple words

As transistors scale linearly, so the signal currents scale in proportion to area, but the physical separation between signals scales linearly, as does the length of the interconnections, so the internal EMI remains in the same proportion.

 

[Baluncore]

Everything gets smaller.
All at the same time.
Including the EMI.

 

[TonyStewart]

As i recently came to know that the energy is not travelled in the wire infect it is travelled in the space around the wire in the electrical and magnetic field (thanks to varitasium for his video) so my question is particularly related to the IC fabrication.

In IC fabrication we have micro-scale deployment of transistors and wire connections. On a single dice which is smaller than the palm has millions of transistors, so it means that the these connections and transistors have very close space to each other so at such small scale if the energy is delivered in space then it means that this energy must have interfered with the other metal connections energy so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?

I disagree with the Veritasium video. The energy flows into the conductor's distributed inductance and returns thru the distributed dielectric. The phase of all the continuous spectrum of a step pulse current is 180 deg out of phase between L & C.

If all the energy travelled thru the dielectric, then you could replace conductors with sparkplug wire say at 50 kohm/m vs copper at say 50mOhm/m (a million times difference. ) then the current will not change. But it does, so this is false. A 25 kV spike will not create half a million amps. If there was no Inductance in the wire, then the Zo would be 0 and then if the source was also near 0 Ohms, it could be a million amps. But you can never have 0 inductance in a long wire. Because then the length/width ratio would also have to be 0.

The impedance depends on both the CONDUCTION current in the wire inductance and the return from the DISPLACEMENT current in dielectric from the change in E-Field. It takes both L&C with their respective lossy resistance to transfer the energy in a transmission line with a characteristic impedance of Zo.

$$Z_o= \sqrt{\frac{R_s+L}{G_p+C}}$$

None of the energy is stored in conductor resistance, but it is all stored in +/- reactance, namely the distributed inductance and capacitance so the energy is equal in both elements but out of phase by 180 degrees with respect to each other. Thus over one cycle of all frequencies the reactance cancels out before the reflections (if they occur). So the Zo initially behaves like pure lossless resistance if you ignore Rs, Gc and the load until the reflection occurs and all energy is shared in the distributed L & C equivalent lumped element equivalent circuit.

The propagation delay in a silicon dielectric might be around 15 um / ps so for < 1 um CMOS the path length is not the cause of the delay rather it is the junction capacitance from lower RdsOn and gate gaps. Thus the breakdown voltage perhaps of 75kV/mm or 75V/um you have a severe deionization challenge when depositing 5 nm gap CMOS!! This is one of the major challenges in yields not just from lithographic resolution but from controlling the e-fields to prevent junction arcs or breakdown in sub-microsec times.

Just like PCB's EMI crosstalk exists and conductor orientation and metalization coplanar ground tracks will reduce driver internal emissions as well as layer optimizations.

 

[Baluncore]

The energy flows into the conductor's distributed inductance and returns thru the distributed dielectric. The phase of all the continuous spectrum of a step pulse current is 180 deg out of phase between L & C.

Not in my universe.

That 180° phase shift is only for the magnetic field that enters the conductor surface, which cancels the incident field into the conductor, and makes the surface of the conductor a mirror that guides energy propagation parallel to the surface. Energy that diffuses through the surface of an imperfect conductor is lost as heat.

The electric field is in phase with the magnetic field in the space between the guide conductors. That must be so, as the Poynting vector points parallel to the conductive surface, in the direction of the load, on the outside of a perfect conductor.

All signals inside an IC travel through the insulating dielectric of a transmission line, guided between multiple conductors, be it a conductive trace above a ground-plane, or a differential pair.

 

[TonyStewart]

Not in my universe.

That 180° phase shift is only for the magnetic field that enters the conductor surface, which cancels the incident field into the conductor, and makes the surface of the conductor a mirror that guides energy propagation parallel to the surface.

Your universe in not wrong, nor am I, I think you misunderstood.

- Let me expand/ explain with a simulation, that you should immediately recognize as a lumped model of Telegrapher's Transmission Line above an ideal transmission line with same Zo and delay.

- current of L's is 90 deg lagging, current out C to ground is 90 deg leading for every discrete frequency. Thus the phase between L&C is 180 deg while from input voltage to input current is 0 degrees.

https://tinyurl.com/2xqtkkml example of lumped model 20th order 0.5 us 50 ohm and 50 ohm ideal delay line 0.5 us delay. Same step current similar delay.

some ripple.

 

[Baluncore]

Hey brother, can you please write in simple words

I disagree with the Veritasium video. The energy flows into the conductor's distributed inductance and returns thru the distributed dielectric.

The idea that energy goes one way in the inductance, then another way in the dielectric is simply wrong and confusing. It does not surprise me that you disagree with Veritasium.

The energy is launched down the transmission line as an EM wave. That EM wave energy, is guided through the dielectric by the presence of the conductors.

 

[TonyStewart]

The idea that energy goes one way in the inductance, then another way in the dielectric is simply wrong and confusing. It does not surprise me that an anarchist disagrees with Veritasium.

The energy is launched down the transmission line as an EM wave. That EM wave energy, is guided through the dielectric by the presence of the conductors.

_{Spare the personal remarks which give you a poor s11 factor.}
We are talking about charge flow right? Veritasium failed to even mention wave resistance or Telegrapher's equations or impedances and just did hand waving diagrams that were Mickey Mouse for a broad audience. Although he is the best animator and a most interesting podcaster.

The dielectric controls the speed = true, but the L/C ratio = controls the rate of change of charge flow i.e. V/Zo.

Do you need proofs? I trust you will correct your assumptions.

Did you examine my simulation?
The 180 deg polar plots of L vs C current? That should prove what I said alone.

You do realize you cannot have transmission line effects without inductance, I trust.

 

[TonyStewart]

Hey brother, can you please write in simple words

What he means is L and C which store, react and radiate EMI is scalable comparing PCBs, hybrids and IC's , since L is based on log( length/width ratio) and C is based on area/gap ratio. So it is scalable for EMI.

Yet IC's are many more layers so it is 3D yet higher impedance, but when many transitions are synchronous, it can add up to a very low ESR 25 ohms/N and pF*N with high nF loads, so layout is critical.

Since L in short lengths (we call effective series inductance or ESL) can be ~ 0.5nH/mm, having low ESR Caps near IC pins is critical to reduce contaminating other IC's with current spikes in LC resonant decoupling caps, with one per CMOS IC. Imagine that the Cap, value should be 100 times more than the most pF being switched from Coss, Ciss in the IC for each transistor switching at exactly the same time. But also don't forget the cap ESR can drop voltage (I*ESR) just as the C ratio of all the FETs in a circuit that are synchronous can drop decoupling cap voltage
TTL did not have this pF spike issue so it was 1 Cap per 10 IC's.

Sorry if this is outside your fabrication question, I don't know all those details that you are expecting.

 

[Baluncore]

We are talking about charge flow right?

No, we are talking about energy transfer. It cannot be charge transfer because the transmission line has a sum-zero total current.

The presence of an EM field on the line influences electrons on the surface of the conductors. That charge movement is local, and secondary to the energy transfer along the line. Those surface currents are a function of the strength of the magnetic field being reflected from, so being guided along the line. The voltage between the conductors is a function of the strength of the electric field being guided by the line. The energy being propagated is the Poynting vector, the cross product of E and M.

Children are taught that the energy is carried by the electrons in the wires. They measure the voltage between conductors, which is a proxy for the E field, and they measure the current in one wire, which is a proxy for the M field. The product of the voltage and current is the power, but it is really the cross product of E and M.

 

[Baluncore]

Did you examine my simulation?

No I did not. You edited it after I received the notification and read the post.
It appears to be off-topic and irrelevant to the thread.

The 180 deg polar plots of L vs C current? That should prove what I said alone.

I don't understand why you are trying to confuse this thread and make it so difficult. It does not matter how self-righteous you are. We all need to avoid the confusion you are espousing.

You do realize you cannot have transmission line effects without inductance, I trust.

I really find that very hard to believe.

 

[berkeman]

Thread closed temporarily for Moderation...

 

[berkeman]

Okay, after some cleanup, the thread is reopened. Thanks for your patience.

 

[berkeman]

In IC fabrication we have micro-scale deployment of transistors and wire connections. On a single dice which is smaller than the palm has millions of transistors, so it means that the these connections and transistors have very close space to each other so at such small scale if the energy is delivered in space then it means that this energy must have interfered with the other metal connections energy so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?

Here is a good article from the people that help us simulate EMI and Crosstalk in IC structures:

https://resources.system-analysis.cadence.com/blog/msa2022-emi-and-crosstalk-in-integrated-circuits