How to improve synchronous counter

[KillaKem]

Assume a synchronous counter with the following counting
sequence:
0 -> 1 -> 3 -> 2 -> 4 -> 6 -> 5 -> 7 -> 0

1.Produce the above counter next state equations.

2.Using positive-edge D-type flip-flops, 2-input OR and 2-input AND gates, sketch the circuit diagram of the above counter.

3.Given that, a D-type flip-flop has TPHL= 10 ns, TPLH= 8 ns, Tsu=2 ns, a 2-input AND gate has propagation delay of 3 ns, and a 2-input OR gate has propagation delay of 5 ns, estimate the maximum clock frequency at which the above counter could operate.

4.Describe how the complexity of the given counter could be reduced by using a different count sequence.

****I have done the first three questions, the only problem I have is in answering the last question.I really don't understand what the question is looking for.

 

[Valkarie]

1.Produce the above counter next state equations:Q(n+1) = Q(n) XOR (Q(n) AND Q(n-1))2.Using positive-edge D-type flip-flops, 2-input OR and 2-input AND gates, sketch the circuit diagram of the above counter:Q(n+1) = D FF Q(n) OR (Q(n) AND Q(n-1))3.Given that, a D-type flip-flop has TPHL= 10 ns, TPLH= 8 ns, Tsu=2 ns, a 2-input AND gate has propagation delay of 3 ns, and a 2-input OR gate has propagation delay of 5 ns, estimate the maximum clock frequency at which the above counter could operate:Maximum Clock Frequency = 1/((Tsu + TPHL + TPLH + (2*3) + (2*5)) * 10^-9) = 1/(38 * 10^-9) = 26315789.47 Hz4.Describe how the complexity of the given counter could be reduced by using a different count sequence:The complexity of the counter can be reduced by using a simpler counting sequence, such as 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 0. This reduces the number of logic gates required to implement the counter, and thus reduces the overall complexity.