Mealy FSM Edge Detector Code Problems

[Xinthose]

Homework Statement

Create a Mealy Edge Detector, then measure the pulse width of 75 micro seconds by 50 MHz clock; here is the timing diagram:

I am basically trying to emulate this diagram in my test fixture code (using Xilinx 14.1 in Verilog) and am having errors. Also, the tick is supposed to be a push button on my FPGA Board I think; any help would be greatly appreciated as my professor won't help me. The book doesn't help and he tells me to just figure it out, so that is what I am trying to do here. Where you see my clock there, that is my attempt at making it alternate like in the picture, I don't know how to do it.

module Homework_3_Mealy_Edge_Detector_TF;

	// Inputs
	reg clk;
	reg reset;
	reg level;
	integer i;

	// Outputs
	wire tick;

	// Instantiate the Unit Under Test (UUT)
	Homework_3_Mealy_Edge_Detector uut 
		(
		.clk(clk), 
		.reset(reset), 
		.level(level), 
		.tick(tick)
		);
	
	initial
	
	begin
		clk = 1'b0;
		#100;
	end
	
	begin
		for(i = 0; i < 8; i = i + 1)
			begin
				level = 1'b0;          // ERROR MESSAGE
				if (level)
					begin
					level = 1'b0;   // ERROR MESSAGE
					#300;
					end
				else
					begin
					level = 1'b1;
					#300
					end
			end
			begin
				clk = 1'b0;
				if (clk)
					begin
					clk = 1'b0;      // ERROR MESSAGE
					#100;
					end
				else
					begin
					clk = 1'b1;
					#100
					end
			end
	end
	
endmodule

also, here's the behavioural model if you're interested, it gives no errors (it's straight from the book)

module Homework_3_Mealy_Edge_Detector
	(
	input wire clk, reset,
	input wire level,
	output reg tick
   );
	
	// symbolic state declaration
	localparam zero = 1'b0,
					one = 1'b1;
		
	// signal declaration
	reg state_reg, state_next;
	
	//state register
	always @(posedge clk, posedge reset)
		if (reset)
			state_reg <= zero;
		else
			state_reg <= state_next;
			
	// next-state logic and ouput logic
	always @*
	begin
		state_next = state_reg;	// default state: the same
		tick = 1'b0;				// default output: 0
		case (state_reg)
			zero:
				if (level)
					begin
						tick = 1'b1;
						state_next = one;
					end
			one:
				if (~level)
					state_next = zero;
			default: state_next = zero;
		endcase
	end

endmodule

 

[LightHero]

</code>A:The main issues with your code appear to be that the clk and level variables have not been declared as registers, and you are using blocking assignments.Try the following, which should fix those problems.<code>module Homework_3_Mealy_Edge_Detector_TF; // Inputs reg clk; reg reset; reg level; integer i; // Outputs wire tick; // Instantiate the Unit Under Test (UUT) Homework_3_Mealy_Edge_Detector uut ( .clk(clk), .reset(reset), .level(level), .tick(tick) ); initial begin clk = 0; #100; end always @(posedge clk) begin if (reset) begin for(i = 0; i &lt; 8; i = i + 1) begin level &lt;= 0; #300; end end else begin clk &lt;= ~clk; #100; if (clk) begin level &lt;= 1; #300; end else begin level &lt;= 0; #300; end end endendmodule</code>