Quadrature sampling detector circuit

In summary, the purpose of the 2.5 VDC offset fed into the center tap of the transformer is to provide a bias for the 4x bus switch, which can only pass signals between 0V and 5V. The 47 nF capacitors act as a holding function for the sample and hold action, charging during the sampling period until it reaches 2.5V. They will also filter out most of the sampling frequency, so if using a 5 MHz sampling frequency, it is recommended to reduce the capacitor value to 10nF.
  • #1
FrankJ777
140
6
Hi. I'm trying to build a quadrature sampling detector, or Tayloe detector based on the design at http://garage-shoppe.com/wordpress/?p=371 . I intend to feed the I and Q signals into a ADC that uses a 1.65V reference. One thing I'm confused about is the purpose of the 2.5 VDC offset fed into the center tap of the transformer. It comes a voltage divider that halves the 5 V VDD, below is a circuit diagram I origionally assumed it's purpose is to provide an offset for an ADC but I'm not sure. The 47 nF capacitors are supposed to provide the "holding function" of the sample and hold action, but I'm not sure if the voltage on them will ever be 2.5V as the caps wouldn't have time to charge durring the sampling period. It also seems that the signal out of the 4 x bus switch would be a 2.5V pulse at the sampling frequency. Would the capaitors filter those out. According to my Bode plot for my corner frequency is about 3MHZ, and I'm trying to use a 5 Mhz sampling frequency. Am I looking at this all wrong? Thanks for the help in advance.
http://garage-shoppe.com/wordpress/wp-content/uploads/2010/03/Image4.jpg.
 
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  • #2
FrankJ777 said:
One thing I'm confused about is the purpose of the 2.5 VDC offset fed into the center tap of the transformer. It comes a voltage divider that halves the 5 V VDD, below is a circuit diagram I origionally assumed it's purpose is to provide an offset for an ADC but I'm not sure.
Look at your 4x bus switch. Its power supply is only 5V. That means it can only pass signals between 0V and 5V. In order to pass signals with the maximum peak to peak voltage, it needs to be biased to half the supply voltage

FrankJ777 said:
The 47 nF capacitors are supposed to provide the "holding function" of the sample and hold action, but I'm not sure if the voltage on them will ever be 2.5V as the caps wouldn't have time to charge durring the sampling period.
The I_Out and Q_Out lines should be very high impedance so the primary means of their discharge is back through the bus switch when it is closed. The capacitor may not completely charge during the sampling period but it will continue charging during the sample until it reaches 2.5V. If the bias plus signal is higher than 2.5V it will charge to more than 2.5V. When the signal plus bias is less than 2.5V the capacitor will discharge through the switch.

FrankJ777 said:
It also seems that the signal out of the 4 x bus switch would be a 2.5V pulse at the sampling frequency. Would the capaitors filter those out. According to my Bode plot for my corner frequency is about 3MHZ, and I'm trying to use a 5 Mhz sampling frequency. Am I looking at this all wrong? Thanks for the help in advance.
http://garage-shoppe.com/wordpress/wp-content/uploads/2010/03/Image4.jpg.
Yes the capacitors will filter out most of the sampling frequency. If you want to use a sampling frequency of 5 MHz, I would reduce the value of the capacitors to 10nF to start.
Only if the sampling voltage is too noisy or sags too much during the sampling period would I increase the value.
 

What is a quadrature sampling detector circuit?

A quadrature sampling detector circuit is a type of circuit used in radio frequency receivers to convert an incoming signal into a baseband signal. It utilizes two mixers and two local oscillators to sample the incoming signal at two different phases, resulting in a more accurate and efficient demodulation process.

How does a quadrature sampling detector circuit work?

The circuit uses two mixers, one for in-phase sampling and one for quadrature sampling. The incoming signal is split into two paths, with one path being delayed by 90 degrees. The two paths are then mixed with two local oscillators, resulting in a baseband signal with both in-phase and quadrature components. These components are then combined to obtain the original signal.

What are the advantages of using a quadrature sampling detector circuit?

This type of circuit offers better sensitivity and selectivity compared to other demodulation techniques. It also eliminates the need for an additional filter, reducing the overall complexity and cost of the receiver. Additionally, quadrature sampling allows for simultaneous demodulation of multiple signals.

What are the limitations of a quadrature sampling detector circuit?

The circuit requires precise phase and amplitude balance between the two mixers and local oscillators, making it more sensitive to component variations. It is also affected by local oscillator leakage, which can cause interference and distort the demodulated signal. Additionally, it is not suitable for signals with high amplitudes or significant phase noise.

What are some applications of a quadrature sampling detector circuit?

This type of circuit is commonly used in radio frequency receivers, especially in software-defined radio systems. It is also used in communication systems for satellite and cellular networks, as well as in radar and radio astronomy applications.

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