Subharmonic noise in DC-AC H-bridge Inverter

[J-the]

I have a design for a DC-AC full H-bridge inverter implemented with IGBTs that is functioning quite well, but there is one problem that I am having trouble solving. I am seeing spikes in the FFT of the output noise floor that appear to be subharmonics of the PWM frequency.

I am measuring the noise floor by setting the AC output of the inverter to 0V, and I calculate the FFT of the 0V output. See the image below for an example of my noise floor with apparent subharmonic spikes.

The fundamental frequency of the PWM for this system is 18kHz.
Notice in the image above that there are strong peaks at 18kHz, 36kHz, 54kHz, and 72kHz. These spikes are expected because they are the fundamental frequency and the harmonics.

Also notice the peaks at 2.25kHz, 4.5kHz, 9kHz, and 13.5kHz. 18000/8 = 2250
It appears that some of these noise spikes could be subharmonics of the 18kHz fundamental, but they could also be regular harmonics of the 2.25kHz subharmonic.

I have done a lot of testing and I am pretty confident that the problem is with the PCB I have designed or the problem is with the IGBT driver modules (mounted on this PCB). This PCB distributes the PWM signals to the IGBT driver modules, and it has a microprocessor and supporting circuitry to perform system monitoring and data collection.

I still have not been able to determine the exact source of this noise. I also have not been able to determine how it is getting into my PCB.

Any suggestions on how to clean up these subharmonic noise spikes would be appreciated. Any suggestions for how to determine what is transmitting this noise, or how the PCB is receiving this noise would also be helpful.

 

[anorlunda]

Is there any sampling involved? If so, then aliasing is the first thing that comes to mind.

 

[J-the]

I do not think that aliasing is an issue with my FFT measurement. The data for the FFT is sampled at 192kHz.

The 2.25kHz, 4.5kHz, etc. subharmonic frequencies in the noise floor do not seem to be an alias of any meaningful frequencies with this sample rate. I might be miscalculating something though.

The PWM signal is generated by using a comparator with a triangle wave. Could there be aliasing with this PWM method?

 

[anorlunda]

Most nonlinearities, such as saturation, cause harmonics, not sub-harmonics.

The PWM signal is generated by using a comparator with a triangle wave. Could there be aliasing with this PWM method?

Is is possible that the comparator has a reponse time (or jiggle in the comparator's time) that approached the period of the comparator wave? That could cause aliasing in the circuit.

Could you experiment with the triangle wave frequency? If the sub-harmonics are insensitive to that frequency, it would rule that out as a possible cause.

 

[Baluncore]

The integer harmonics of the fundamental, (lets call them super-harmonics), are expected because your signal is rectangular, not sinusoidal. For rectangular signals you should expect the odd harmonics to be most significant.

Sub-harmonics are also expected in SMPS, but are generated by a quite different processes.
Fundamentally, sub-harmonic generation requires the storage of energy or information for times longer than the period of the fundamental.

With a SMPS, as energy is taken from the real input reservoir, there may be an instability where alternative pulses vary in energy and time. For example, taking more energy this time, results in a lower reservoir and less energy for the next pulse, which then reinforces the pattern. Much more complicated sequences of dance steps are possible, all the way to chaotic noise.
Where a load taking power from the SMPS output varies in a regular way, it can interact with the SMPS period to generate a beat, that beat can phase-lock to a sub-harmonics.

A digital divider composed of flip-flops generates sub-harmonics of the digital input.
A step charge pumped capacitor, reset by a UJT or tunnel diode, is also a sub-harmonic generator.

Since sub-harmonics divide the fundamental, they can cross-modulate in non-linear components to make non-integer super-harmonics.

 

[J-the]

Is is possible that the comparator has a reponse time (or jiggle in the comparator's time) that approached the period of the comparator wave? That could cause aliasing in the circuit.

Could you experiment with the triangle wave frequency? If the sub-harmonics are insensitive to that frequency, it would rule that out as a possible cause.

The subharmonics do follow the triangle frequency. I have already looked a little into the comparator/PWM generator, and I did not find anything conclusive. It sounds like it might be worth digging a little deeper into this part of the circuit to be certain that this is not the source of my problem.

This new design that I am working on is based off of an old design that does not exhibit this subharmonic problem. The two designs have identical PWM generating circuit. The DC input reservoir is nearly identical on the two designs. The PCB is significantly different between the two designs, which is why I have been focusing on possible noise problems with this portion of the design.

 

[Baluncore]

Without seeing your PCB layout it is difficult to guess what might be wrong. Maybe there is a problem with the ground plane layout, or the path taken by the control and signal currents is now partly shared with the IGBT gate drive currents. What is the supply load during testing?

 

[J-the]

What is the supply load during testing?

The the noise floor image in the original post is with the output of the supply is connected to a resistor load. I see the same subharmonic noise when the output is connected to an inductive load.

Maybe there is a problem with the ground plane layout, or the path taken by the control and signal currents is now partly shared with the IGBT gate drive currents.

The gate drive signals are driven by an off-the-shelf isolated IGBT driver module. This module is mounted to the same PCB as the low voltage supporting circuitry. The IGBT driver output area is isolated from the rest of the PCB signals. The power and ground planes are not filled in this isolated area.

The layer stackup for my PCB is shown below. The low voltage (5V logic) PWM traces to the IGBT driver inputs are routed on layers 1 and 6.