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SpaceCreature
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I have a question about S-R latch for a specific diagram below (no, this is NOT a homework question).
Is there something, physically, about the way that AND (or even other) gates are built that once they know one input, they know what the output will be? I know, for example, that if R = 0, the output of AND will be 0, because both inputs need to be 1 or high for the output to be 1. I'm guessing the answer is no, the circuit does not know what the output will be with one input because if R = 1, how do we know what the second input will be?
What boggles my mind is this: let's pretend that R always gives its output first, because for some reason there is a delay in S. How is this possible? How can there even be an output for either AND gate if the AND gate needs two inputs to make a decision about an output?
http://img839.imageshack.us/img839/3791/latchq.jpg
Is there something, physically, about the way that AND (or even other) gates are built that once they know one input, they know what the output will be? I know, for example, that if R = 0, the output of AND will be 0, because both inputs need to be 1 or high for the output to be 1. I'm guessing the answer is no, the circuit does not know what the output will be with one input because if R = 1, how do we know what the second input will be?
What boggles my mind is this: let's pretend that R always gives its output first, because for some reason there is a delay in S. How is this possible? How can there even be an output for either AND gate if the AND gate needs two inputs to make a decision about an output?
http://img839.imageshack.us/img839/3791/latchq.jpg
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