Why Does My Verilog Code Not Simulate m2 and m13 as Expected?

In summary, the conversation discussed simplifying a given function using Karnaugh mapping. The resulting functions were tested and entered into Quartus, but did not produce the expected output. After reviewing the provided Verilog code, it was determined that there were errors in the code and a correct version was provided.
  • #1
unknown_2
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Homework Statement


given the midterm function:
f= m1 + m2 + m3 + m6 + m7 + m10 + m13

-supposed to simplify this function

Homework Equations



N/a

The Attempt at a Solution


i got the following functions using Karnaugh mapping:
f = [tex]\overline{x_{1}} \cdot \overline{x_{2}}[/tex] + [tex]\overline{x_{1}} \cdot x_{3}[/tex] + [tex]x_{1} \cdot x_{2} \cdot \overline{x_{3}}\cdot x_{4}[/tex] + [tex]\overline{x_{4}}\cdot x_{3}}[/tex]

I tested it out by hand and it seemed fine to me, once i entered into Quartus and simulated a functional wave, m2 and m13 did not come out to 1 like it's supposed to.

Verlog code i used:
Code:
module design_1 (x1,x2,x3,x4,f);
	input x1, x2, x3, x4;
	output f;
	assign f =(~x1 | ~x2 | ~x3 | x4) & (~x1 | ~x2 | x3 | ~x4) & 
	(~x1 | ~x2 | x3 | x4) & (~x1 | x2 | x3 | ~x4) & (~x1 | x2 | x3 | x4) & 
	(x1 | ~x2 | x3 | ~x4) & (x1 | x2 | ~x3 | x4);
endmodule

can someone please tell me where i went wrong?

any help would be appreciated
thanks in advanced,
 
Last edited:
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  • #2
Your Verilog code is incorrect. It should look like this:module design_1 (x1,x2,x3,x4,f); input x1, x2, x3, x4; output f; assign f = (~x1 & ~x2 & ~x3 & x4) | (~x1 & ~x2 & x3 & ~x4) | (~x1 & ~x2 & x3 & x4) | (~x1 & x2 & x3 & ~x4) | (~x1 & x2 & x3 & x4) | (x1 & ~x2 & x3 & ~x4) | (x1 & x2 & ~x3 & x4);endmodule
 
  • #3


I would like to commend you for using Karnaugh mapping to simplify the given function. However, it seems that there may be an error in your Verilog code. Upon inspecting your code, I noticed that you have used the bitwise OR operator (|) instead of the logical OR operator (||). The bitwise OR operator will result in a 1 only if both inputs are 1, whereas the logical OR operator will result in a 1 if either input is 1. This may be the reason why m2 and m13 are not coming out as 1 in your simulation.

I would suggest editing your code to use the logical OR operator and then simulating again to see if it produces the correct output. Additionally, you could also double check your Karnaugh map and make sure that you have correctly grouped and simplified the terms.

I hope this helps and good luck with your homework!
 

Related to Why Does My Verilog Code Not Simulate m2 and m13 as Expected?

1. What is a digital circuit?

A digital circuit is an electronic circuit that operates on discrete values or binary digits (0 and 1). It is the fundamental building block of digital electronics and is used to process and store information in the form of digital signals.

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A digital circuit works by using logic gates to manipulate and process binary data. These logic gates, which can be made up of transistors, perform operations such as AND, OR, and NOT on the input signals to produce an output signal based on the logic of the circuit.

3. What are the main components of a digital circuit?

The main components of a digital circuit include logic gates, flip-flops, multiplexers, decoders, and registers. These components work together to perform various operations on digital signals and store data.

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A combinational digital circuit produces an output based solely on the current input values, while a sequential digital circuit also takes into account the previous input values. This means that sequential circuits have the ability to store data and perform more complex operations.

5. How are digital circuits used in everyday technology?

Digital circuits are used in a wide range of everyday technology, such as computers, smartphones, and televisions. They are also used in communication systems, control systems, and other electronic devices that require processing and storage of digital signals.

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