10mhz - which is typical at most companies I think, but I'd like to look into improving that, more specifically to see if there's anything I can do about the half-cycle limitation from the posedge->negege nature of flopping the values into the final TDO register.
Thanks for your help!
I'm not too sure what the clock tree look like (somebody else did that part), but the chip is quite big and has many partitions, so I believe we have an entry point into each partition and then branches out to different logic within the partition that needs the clock.
Also because of the...
I'm trying to design a synchronous logic that uses a negative edge flop to shift data out of a chip (as part of the IEEE1149.1 standard). The input to this negedge flop is muxed from a whole bunch of shift registers within the chip, and these registers are all on posedges.
Ideally, if...