Recent content by Zeuss1220

Hey guys. I'm completing my Year 2 in E&E engineering next month, and due to some logistic reasons, I won't be able to do any internships this summer, instead I'll be doing it next summer. I've decided to work on some project during the summer. I could get something productive on my CV and...

For this simulation, load current absorption is to be assumed as 0.5A, hence 30 Ohms load resistor. I get no difference in outpt for op amp resistor value varied to different kOhm values. Like I mentioned earlier, values in the tens or hundred ohms give me a convergence error. I'll assume the...

Low ohms give me convergence errors. Not sure what it actually means though, came across it numerous times working with this circuit.

Adding a high value resistor at the base of the darlington pair seemed to do the trick. Even at 50V op amp supply, sufficient voltage is required from the source to provide an output voltage of 15V. I used an 8k resistor, are there any recommended value I should use instead? From what I...

References: http://tangentsoft.net/elec/opamp-linreg.html http://www.tubecad.com/2009/09/blog0172.htm

@gneill I understand what you're trying to say, and I see how that's sensible in practice. But I was specifically instructed to use an Ideal Op Amp for simulation. As for the reference voltage, I have no other idea besides a DC source. I'm not sure whether using another "source" in the model...

The only parameters of the OpAmp I can change is its supply. I tried setting it at 5V, but it is limiting the output voltage. Source: 30V dc Input without rectifier. Op amp supply: 5V Output votlage: 4.05V The BJT is not "*drawing current" from the source. The BJT supposed to be a current...

The ideal Op amp should be an feedback error amplifier. So should I set the supply voltage lower? or is there a problem with regulator model design?

It has something to do with the diode and the op amp. The power to the output comes from the OpAmp supply. During the test without the rectifier, the input(Vin) of the regulator is connected directly to the source(VSIN). So Vin must = VSIN. So the source is the one limiting the output voltage...

There's 15.68V DC at the input side, with or without the smoothing cap (in fact with or without the input bypass cap too).

I'm using a LM[Three-One-Seven] to regulate dc voltage output from mains power(240V ac). For PSPICE simulation, I was instructed to use an ideal OpAmp and Darlington BJT to model the IC in PSPICE. I came up with the following model, which satisfies the equation Vo=Vref(1 + RL/RH), where Vref =...

Yes. But I don't how what characteristic differences they represent.

So how do you think I should answer the 3 questions above? What are the characteristic differences involved?

1.CMOS: 0mA, TTL: -0.2mA 2. (Voltages used: 3.5V, 3.25V, 3.0V) CMOS: 3.3mA, 3.6mA, 4.0mA. TTL: 0.06mA, 18.6mA, 27.1mA 3. CMOS: 2.68V, TTL: 1.025V I'm not sure what to deduce from these

Homework Statement We just did an experiment on the input and output characteristics of TTL and CMOS NAND gates. We recorded the following data for each of the two gates. 1) Input Threshold Voltage 2) Input Current(for input logic 1 and 0) 3) Output Voltage(for output logic 1 and 0) 4)...