Comparing TTL and CMOS Gate Characteristics

[Zeuss1220]

Homework Statement

We just did an experiment on the input and output characteristics of TTL and CMOS NAND gates. We recorded the following data for each of the two gates.
1) Input Threshold Voltage
2) Input Current(for input logic 1 and 0)
3) Output Voltage(for output logic 1 and 0)
4) Output Sourcing Current(for 3 voltages)
5) Output Sinking Current

We haven't had the lecture on this topic so I'm quite unclear about this. We are required to compare both devices with regard to:
i) input threshold voltage and measured input current for logic 0 input
ii) output voltage for logic level 1 and 0
iii) sourcing current and sinking current

Homework Equations

The Attempt at a Solution

From what I've read online, CMOS is said to have low power consumption. But i don't know how to apply this information to answer my questions. I would like to know some basic infomation related to this topic and the question so I can answer these question by looking at my own data.

Thanks.

 

[uart]

Tell us what differences you noticed in:

1. Input current for logic 0.

2. Output sourcing current.

3. Input high threshold voltage.

 

[Zeuss1220]

Tell us what differences you noticed in:

1. Input current for logic 0.

2. Output sourcing current.

3. Input high threshold voltage.

1.CMOS: 0mA, TTL: -0.2mA

2. (Voltages used: 3.5V, 3.25V, 3.0V) CMOS: 3.3mA, 3.6mA, 4.0mA. TTL: 0.06mA, 18.6mA, 27.1mA

3. CMOS: 2.68V, TTL: 1.025V

I'm not sure what to deduce from these

 

[NascentOxygen]

I'm not sure what to deduce from these

Not much at all as far as power efficiency goes. You really needed to measure the current drawn from the power supply under various conditions to be able to make an enlightened comparison of power demands.

But with the lab's purpose being to compare thresholds and drive capabilities, you are not really looking at power efficiency.

 

[Zeuss1220]

Not much at all as far as power efficiency goes. You really needed to measure the current drawn from the power supply under various conditions to be able to make an enlightened comparison of power demands.

But with the lab's purpose being to compare thresholds and drive capabilities, you are not really looking at power efficiency.

So how do you think I should answer the 3 questions above? What are the characteristic differences involved?

 

[uart]

1.CMOS: 0mA, TTL: -0.2mA

2. (Voltages used: 3.5V, 3.25V, 3.0V) CMOS: 3.3mA, 3.6mA, 4.0mA. TTL: 0.06mA, 18.6mA, 27.1mA

3. CMOS: 2.68V, TTL: 1.025V

I'm not sure what to deduce from these

Those are some pretty significant differences in input-loading, output current sourcing, and input threshold. Yes?

 

[Zeuss1220]

Those are some pretty significant differences in input-loading, output current sourcing, and input threshold. Yes?

Yes. But I don't how what characteristic differences they represent.

 

[NascentOxygen]

Yes. But I don't how what characteristic differences they represent.

There is an important term "fan out". (Try googling it.) Address that as it applies to your two different logic gate technologies.