Why Must Gate Current Be Avoided in n-Channel JFETs?

[kthouz]

Hi! I am learning this topic of the electronics and they say that "for an n-channel Junction FET, gate current is to be avoided; consequently the gate-channel junction is never foward biased". My question is why that gate current has to be avoided?

 

[MATLABdude]

Take a look at the pictures under the "Structure and channel formation" section of the Wikipedia article:
http://en.wikipedia.org/wiki/Mosfet#MOSFET_structure_and_channel_formation

At low frequencies, the silicon dioxide layer underneath the (metal) Gate (G) electrode electrically insulates the gate from the p-type substrate, and you get no current flowing from the Gate to any of the other terminals. In fact, that's where the FET gets its name from: putting charge on the gate oxide "pushes" charges deeper into the substrate and allows a conducting channel to form between the source and drain. It's the electric Field from the gate oxide which Effects the Transistor action. The particulars of the above discussion apply only to enhancement type FETs, which are the vast majority of FETs in use (as opposed to a depletion type FET which has the channel "built-in", requiring you to do the opposite of the above and narrow/shut-off this conducting channel).

You may ask whether or not it's possible to put current between the substrate (source substrate terminal, SS) and either the Source (S) or Drain (D), and the answer is yes! However, your chunk of silicon will be working like a diode, instead of a FET.

 

[kthouz]

If i did understand there have to be some charges supplied to the substrate to allow conduction and these charges are from the gates. Where they have been pushed from by the gate-source reverse biased voltage. Am i right?

 

[MATLABdude]

If i did understand there have to be some charges supplied to the substrate to allow conduction and these charges are from the gates. Where they have been pushed from by the gate-source reverse biased voltage. Am i right?

In an IDEAL[*] enhancement FET, the charges do not come from the gate electrode. The charges ACCUMULATE on the gate electrode, and the electric field due to these charges attracts (or repulses) electrons in the substrate, it is these electrons (or exposed holes: positive charges) which actually form the channel.

So yes, there are charges which have been 'pushed' into place to form a channel, but these come from the substrate via charge separation, and not from the gate electrode.

EDIT: The threshold voltage is the minimum gate-source voltage required to form the channel in the first place (absent any channel effects).[*] In reality, the oxide is not a perfect insulator and there's a very small leakage current from gate to bulk or other terminals.

 

[kthouz]

thank you.

 

[cabraham]

Regarding forward bias of the gate-source, a JFET is a depletion device, i.e. normal state of "ON". To turn it OFF, the gate must be driven negative wrt the source for n-channel parts.

However, an n-JFET (or p-JFET) can be enhanced to conduct harder. By driving the gate slightly positive (n), the channel is enhanced and the drain current increases above Idss.

But the gate-source terminals form a p-n junction diode. In the reverse direction, or at zero volts, the current is negligible. As the junction is forward biased, the current will increase but does not reach large values until the voltage exceeds 0.50 V. Like all p-n junctions, the I-V curve is exponential. So in order to not incur large gate currents, the G-S voltage should never be driven positive by more than about 0.50 volts. I hope this helps.