Up down Counter Overflow(74191)

[nokeeauser]

Hey guys I am currently building a digital integrator for my senior design project. The project consists of An A/D, UP/DN counter, Adder, Register and DAC. The parts I am using are :
A/D: AD7821
UP/DN: 74191
Adder: 7483
Register: 74198

Im cascading the 74191 and the 7483 to get 8 bit versions. its an 8-bit integrator. The problem I am getting is that when I feed a sine wave into an ADC, then feed the ADC into the up/dn counter, the up/dn counter overflows real fast. Basically what I am trying to do is Count up when the signal is rising, and count down when the signal is falling. I am not sure if I am cascading the counters right or what the problem might be, I've tried many things but am completely stumped... any help would be appreciated. thanks in advance.

 

[Phrak]

It's difficult to tell from your parts list what IC feeds which other IC. I think a general outline would be sufficient. That, not withstanding, you only have 8 bits available. I expect you will overflow the counter in 32 clock cycles or so. You do have a free running clock, right?

 

[nokeeauser]

I have attached a word document with a copy of the simulation that I have used in Multisim. How did you know that the counter will overflow in 32 clock cycles? How can i make it so it does not overflow in 32 cycles, should i use more counters? Or should i use some kind of logic gate and registers instead of using a counter. Like if i were to feed the MSB coming from the ADC into the register, and always comparing the current value of the MSB with the last value, and feeding it into an XOR gate or something, then to an adder, do you think that would work?

 

[berkeman]

And an integrator counts up when the signal is positive (not necessarily "rising"), and counts down when the signal is negative (not necessarily "falling"). Welcome to the PF, BTW.

 

[berkeman]

I have attached a word document with a copy of the simulation that I have used in Multisim.

The attachment didn't seem to work. Try again?

 

[nokeeauser]

yes your right about the integrator counting up when it is positive. that's what i had meant to say :) it was a bitmap image zipped...should work...

 

[berkeman]

Can you provide a simple sequence table that shows the input (make it a small varying signal, not a lot above and below 0V), and show the output of the ADC, and the intermediate and feedback terms of the counters and such? Your circuit is complex enough that you need to tabulate what the expected behavior is for small signals first, and then lower the amplitude of your source down to where you can probe to see if the circuit is tracking your expected values. It also wasn't clear to me how the bleed-off term of the integration is being implemented -- you need some damping coefficient, right?

 

[nokeeauser]

im sorry you just completely lost me. I wouldn't even know how to do that..

 

[berkeman]

im sorry you just completely lost me. I wouldn't even know how to do that..

Well, your first stage is an ADC, right? So assume a small AC signal into the ADC (I don't know the ADC -- does it include its own sample and hold?), and write what the output byte will do in response to the input signal, on a system clock by clock basis. Write out like 16-20 lines of bytes, based on what the input is doing.

Then look at what each stage of the circuit is doing on a clock-by-clock basis with this input. How do you clear all the logic intitially? After that clear, and as the input bytes from the ADC start propagating through, write out what the inputs and outputs values do at each logic block, to verifiy that the integrator is doing what it is supposed to.

And on the damping issue, there has to be some way for any DC bias to bleed off over time, or the integrator will peg out one way or the other. As in an analog integrator, you add a large value resistor in parallel with the integration capacitor...

 

[nokeeauser]

here are the pictures of the circuit and the result i get, maybe that will help

 

[berkeman]

here are the pictures of the circuit and the result i get, maybe that will help

Looks like it's trying to do some things right, but having some issues. What happens if you slow the input sine wave way down? What are the digital values at intermediate places in the circuit? What is causing that reset behavior in the digital output?

 

[nokeeauser]

the input sine wave is at 1 Hz, and 1 Vpp. It is very small. i have made another circuit where i have put a switch on the Registers CLR bit to initially clear it then keep it high. and i have put a switch on the LOAD pin of the counters to initially set it 0, then set it High. it seems like it is only counting up for positive values.

 

[nokeeauser]

here in this circuit i have added(well at least tried to use) 16 bit counter thinking the 8 bit version overflows too fast. then what i have tried to do is take the 2's complement of the MSB coming off the ADC the result is actually the one I posted on the earlier post.

 

[Phrak]

The 32 cycle overflow was just a wild guess on my part assuming a 4 bit ADC averaging a value of maybe 8. Then 256/8=32. But it's moot if you've gone to 16 bits wide. Berckeman's the man, and the schematic is far too blurred on my monitor to even guess at.