In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output which is false only if all its inputs are true; thus its output is complement to that of an AND gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A NAND gate is made using transistors and junction diodes. By De Morgan's laws, a two-input NAND gate's logic may be expressed as AB=A+B, making a NAND gate equivalent to inverters followed by an OR gate.
The NAND gate is significant because any boolean function can be implemented by using a combination of NAND gates. This property is called functional completeness. It shares this property with the NOR gate. Digital systems employing certain logic circuits take advantage of NAND's functional completeness.
The function NAND(a1, a2, ..., an) is logically equivalent to NOT(a1 AND a2 AND ... AND an).
One way of expressing A NAND B is
A
∧
B
¯
{\displaystyle {\overline {A\land B}}}
, where the symbol
∧
{\displaystyle {\land }}
signifies AND and the bar signifies the negation of the expression under it: in essence, simply
¬
(
A
∧
B
)
{\displaystyle {\displaystyle \neg (A\land B)}}
.
NAND gates with two or more inputs are available as integrated circuits in transistor-transistor logic, CMOS, and other logic families.
< Mentor Note -- thread moved to HH from the technical forums, so no HH Template is shown >
a) Using the Yenka (or similar) simulator, you are required to build an RS flip-flop using 2 NAND gates, switches, LEDs and 330Ω resistors. Test the circuit and prove its correct operation against the...
Homework Statement
Draw the logic circuit to represent the following Boolean expression using only NAND gates:
Homework EquationsThe Attempt at a Solution
Is this correct?
Thanks
Homework Statement
(a)
The diagram represents a NAND gate with two inputs, T1 and T2, and an output X. Copy the truth table above and complete it.
Show how a NAND gate can become a NOT gate.
(b)
Draw up a truth table for the combination of NAND gates shown above.
2. The attempt at a...
Homework Statement
Constructing a NAND gate as an inverter.
Homework EquationsThe Attempt at a Solution
I've attached the image at my attempt to construct the circuit. The output is always on, which it should be except when both inputs are zero. Could someone explain what I am doing wrong...
how would yo connect a 2 input nand gate to form a basic inverter?
i constructed a truth table. i know that the two middle ones don't count because the inputs have to be of the same value for an inverter. but what conclusion can i draw from this?
Homework Statement
Question:
Refer to Fig. 6-5. This standard TTL 2-input NAND gate uses ______ (open-collector, totem pole) outputs.
Solution:
The 2-input TTL NAND gate in Fig. 6-5 (which is attached as "TheFigure.jpg") uses a totem pole output configuration.
Homework Equations
N/A...
http://www.dummies.com/how-to/content/electronics-projects-how-to-create-a-transistor-na.html
In the above link it is said that the output is logic ON if both the inputs are OFF.
What does that mean. Correct me if I am wrong.
As far as I have learned from the site was when the input is ON...
We can use NAND gate only to get ( XOR gate ) of 2 input ( A and B ) :
By using (4) NAND gate :
The output of 1'st NAND : (AB)'
The output of 2'nd NAND : ((AB)'.A)' = (A'B)
The output of 3'rd NAND : ((AB)'.B)' = (AB')
The output of the hole circuit will be: ((A'B).(AB'))' = AB'...
Homework Statement
I was looking through some examples in my Digital Logic book and I stumbled across one that gave an answer of x1\uparrow(x2\uparrowx2). The answer I got was x2\uparrow(x1\uparrowx2).
After making a truth table I'm finding that these are not equal solutions. Unless, I'm...
1. Guys how can I draw this equation C.(A(+)B)+ A.B only using Nand gates?
3.I have minimized it but just don't know how to draw it only using Nand gates.
Thanks.
If an AND gate is basically two switches in series, and an OR gate is two switches in parallel, how would you physicaly make a NAND/NOT/NOR gate? What is physically going on in the microchip which has these gates?
I am learning about the implementations of digital logic gates using n-type and p-type transistors.
With the advent of these two transistors, isn't it possible to have more than one implementation of the NAND gate?
Homework Statement
What happens when you place a NOT gate before and after a NAND gate
Homework Equations
Current Research(My own work):
NOT Gate: A NOT gate is also known as an inverter. It is a logic gate which implements a methodology best known in maths as Logical Negation. In other...