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Homework Help: 74138- 3 to 8 decoder hex address help

  1. Nov 6, 2016 #1
    1. The problem statement, all variables and given/known data
    4. FIGURE 1 shows how a 3 to 8 line decoder (74138) can be used in conjunction with NAND gate (74133) to connect a set of switches to the data bus of a microprocessor system via buffers (74367). Answer the following questions relating to the diagram:

    a) What address, in HEX, is required on the address bus in order to read the switches?

    b) RD and MEMRQ are control lines from the CPU. What must their logic state be in order to read the switches?

    Figure 1
    2. Relevant equations

    3. The attempt at a solution
    1.(a) I think the address is A3

    (b) They both have to be low in order to read the switches.

    I have very little knowledge regarding how these components work so would like confirmation or a point out in the right direction please.
  2. jcsd
  3. Nov 6, 2016 #2


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    These datasheets should help with extending your knowledge:
    http://www.ti.com/lit/ds/symlink/sn74s133.pdf [Broken]
    http://www.ti.com/lit/ds/symlink/sn74365a.pdf [Broken]

    Your answer for a) does not look right. What were your thoughts on this?
    Your answer for b) looks right.
    Last edited by a moderator: May 8, 2017
  4. Nov 6, 2016 #3
    Thanks for your reply

    For (a) Im not entirely sure how to interpret the hex address of the "address bits" i.e A0, A15 etc. I think if I understand correctly it is to do with memory maps. It could be something really simple but I don't understand the circuit diagram well enough.
  5. Nov 6, 2016 #4


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    For state of the Input switches to appear on the the Data bus, signals /RD and /MEMREQ have to be in the correct state (which you correctly established). In addition, each address bit needs to be in a specific state (high or low). Break the job into parts:
    0. Understand how the '138 works
    1. What does it look like address bits A15..A4 are doing?
    2. How about A3?
    3. A2..A0?
  6. Nov 6, 2016 #5
    The 138 works as a 3 to 8 bit decoder where 3 inputs can deliver (23) 8 outputs

    For a NAND gate if MEMRQ is low the A15 to A4 have to be high.

    A3 is part of the data enable along with RD and the NAND output.

    A0 to A2 are address lines, part of the ABC logic table where all inputs except one are high

    A0 to A2 select the the lower address of the '138. The other address (A15 to A4) are used to select the memory location or the upper address. Don't know where hex address comes into it. At first I was just converting the outputs of the truth table into hex.
  7. Nov 6, 2016 #6


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    Right. You have determined 12 bits out of the 16 bit address.

    Okay, so what should its state be to enable the '138?

    What output of the '138 are you interested in? What then should A2..A0 be?

    Once you establish the state of all the address bits, you can represent that as a 16-bit binary value. This binary pattern can then be represented a a hexadecimal value.
  8. Nov 6, 2016 #7
    Ok thanks this is the gap knowledge I needed to fill here goes;

    The data output 0 of the '138 is connected to the buffers, so according to the truth table we need ABC to be low in order to connect to the buffers.

    A3 needs to be high to establish the data enable.

    So the 16 bit binary I have is 1111 1111 1110 1000 which in Hex is FFE8
  9. Nov 6, 2016 #8


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    Not right. You correctly said A15..A4 needed to be all high. You are this close.
  10. Nov 6, 2016 #9
    Close indeed! 1111 1111 1111 1000 or FFF8
  11. Nov 6, 2016 #10


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  12. Nov 6, 2016 #11
    Thanks for your help, you have filled a valuable gap in my knowledge too!
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