1. The problem statement, all variables and given/known data 4. FIGURE 1 shows how a 3 to 8 line decoder (74138) can be used in conjunction with NAND gate (74133) to connect a set of switches to the data bus of a microprocessor system via buffers (74367). Answer the following questions relating to the diagram: a) What address, in HEX, is required on the address bus in order to read the switches? b) RD and MEMRQ are control lines from the CPU. What must their logic state be in order to read the switches? Figure 1 2. Relevant equations 3. The attempt at a solution 1.(a) I think the address is A3 (b) They both have to be low in order to read the switches. I have very little knowledge regarding how these components work so would like confirmation or a point out in the right direction please.