ADC/DAC Sample Rate and Reference Voltage

[tomizzo]

I am currently working on a circuit design that is featuring both a ADC and DAC. I'll focus my question on the ADC in this thread.

I'm trying to figure out what each pin does. Am I correct in assuming that the Vref pin on the an ADC chip is used as the maximum encoded value for a voltage? Say for example I have an ADC capable of encoding a 0-5V signal with 8 bits of resolution. And then say that I only want to be measuring a maximum voltage of 2V. If I were to tie 2V to the Vref pin, this should scale the encoded values 0-255 to correspond with voltages from 0-2V. Correct?

However, I noticed on a recent data sheet that the sample rate of the ADC is dependent on the value of Vref (see image below). Why is this? Why would the sample rate depend on what is set to the Vref pin?

Any help regarding this?

 

[dlgoff]

The reference voltage is the maximum value for the conversion as you correctly thought. The rate then would be determined by the size of each chunk of from the 8 bit value. i.e. V_ref/256

 

[tomizzo]

The reference voltage is the maximum value for the conversion as you correctly thought. The rate then would be determined by the size of each chunk of from the 8 bit value. i.e. V_ref/256

Could you expand on why the sample rate is dependent on the value of Vref? Or is the data sheet saying that the sample rate is actually dependent on the value of Vdd which just happened to be the same as Vref?

 

[berkeman]

That's weird. It's not obvious why the sample rate would depend on Vref. I could see it depending a bit on Vdd, but not Vref.

Which chip is it?

 

[tomizzo]

That's weird. It's not obvious why the sample rate would depend on Vref. I could see it depending a bit on Vdd, but not Vref.

Which chip is it?

It is a Microchip MCP3004 (data sheet: http://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf).

The more I look at this, the more I'm starting to assume that the sample rate is dependent on the value of Vdd and not Vref. They simply were listing an example in which case Vdd would be 5.0V or 2.7V in which case the maximum Vref would also have to be 5.0V and 2.7V respectively.

 

[berkeman]

Yeah, that would make more sense. And that's how it's listed in the opening bullets of the datasheet:

• 200 ksps max. sampling rate at VDD=5V
• 75 ksps max. sampling rate at VDD=2.7V

:-)

 

[dlgoff]

But it's a 10 bit ADC. Wouldn't it be faster with 8 bits as opposed to 10 bits? Assuming the same clock rate.

Edit: Okay. Disregard this. I see my mistake. It is V_DD that "determines" throughput.