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16 bit sigma delta ADC question

  1. Jul 19, 2014 #1
    Hi every one,

    I am examining a prototype device that is designed to analyse current from an electrochemical O2 sensor (current source), The sensor will output 1.124 uV per PPM (cross 47 ohms @0.023 uA), and has acuracy of +- 2 PPM, with max 1000 PPM.

    it ueses 16 bit Sigma Delta ADC with 2.5 V Vref ( PIC24FJ128GC006 MCU to be exact ) with 47 ohm resistor across sensor inputs.

    This is my first time seeing 16 bit ADC let along sigma delta, I only know of the 12 bit successive approximation adcs, my question is, despite all the structural diffrences, is it correct to say the step size of this ADC is Vref/2^15 (bipolar) which is 76 uV, and therefore impossible to convert the O2 sensor signal?

    the designer of the devices has used the on chip programable gain to amplify the input by maximum 32 times, which makes it still short of the step size of the ADC.

    what is really puzzlig for me is, if my above calcs are correct, the RAW ADC values should only be noise (≈ 2000 counts )when i apply 20 uA ( ≈1000 PPM ), but the ADC value shoots to 5000 counts, as if it is picking up a signal, where according to my logic it really should not move that much. hence my confusion.

    really appreciate any bodys help on this.
  2. jcsd
  3. Jul 19, 2014 #2


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    76uV / 32 = 2.375 uV, but you need 1.124 uV for 1 ppm resolution.
    Note that: 2.375 uV / Sqrt(4) = 1.1875 uV which is close.
    So, if it averages 4 sequential values it will be very close to meeting a 1ppm specification.

    It relies on the conversion noise to spread the values proportionally into adjacent ADC states.
    The accumulation will then be done with more bits than the ADC.

    My guess is that it accumulates maybe 16 sequential ADC values and produces a 15+4=19 bit total as the result.
  4. Jul 19, 2014 #3
    Thanks for the reply, is the 16 bit in the title not indicating the steps of the quantizer? i saw no mentioning of these calculations in the data sheets. can you elaborate why the / 32 and /Sqrt(4) ?
  5. Jul 19, 2014 #4


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  6. Jul 19, 2014 #5
    I am not the designer, so i cant change any thing. it was designed initially for larger input, but specs changed and it was hurried for the uA sensors, so I have to make sure it works. so far it is very unstable and i want to pin the cause of it, from my knowledge so far it seems the 16 bit just does not have to resolution for the sensor inputs, but I am not so sure that is how the SD ADC works, can I just assume the LSB of the 16 bit is 76 uV ?

    it seems Baluncore is suggesting that is not how it works, and somehow the 16 bit SD ADC is producing 19 bits. I am very confused.
  7. Jul 19, 2014 #6

    jim hardy

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    starting on page 370 of the pic manual is a very interesting section on its sigma-delta ADC

    i had to look up how those things work, and it's not a thing i've ever before run into

    i'd start here

    because that pic manual describes several software controls on resolution (like Baluncore's oversampling ) , and mentions rounding results to 24 bits resolution, see REGISTER 27-2: on page 372 ......

    it's painful using today's sophisticated tools for they are so difficult to learn...

    i'm awed by you young fellows. You seem to be born with intuitive understanding of all that we old guys struggled to comprehend, and you leap forward from there.


    old jim
  8. Jul 19, 2014 #7


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    The PIC24FJ128GC is a microcontroller with an embedded sigma-delta ADC.
    Sigma-delta converters are inherently noisy, the noise depends on controlled parameters.
    I suspect the ADC is being used to produce a huge number of noisy results, see; dithering options.

    DITHER<1:0>: Dither Mode Select bits
    11 = High dither (preferred with higher Oversampling Ratio (OSR) and positive reference well below SVDD)
    10 = Medium dither (preferred for low to medium OSR and positive reference well below SVDD)
    01 = Low dither (preferred when the positive reference is at or near SVDD)
    00 = No dither

    Those dithered results can then be averaged by the microcontroller to produce more accurate estimates.
    Where n samples with statistical noise are averaged, the noise will be attenuated to 1/Sqrt(n).
    So 4 samples will have half the noise, 16 samples will give one quarter of the noise, etc.

    Sampling at 1 kHz, then averaging blocks of 32 samples, will produce 31 estimates per second.
    The noise will be attenuated by Sqrt(32) = 5.6, from 2.375uV to about 0.42 uV, which meets the spec.
  9. Jul 19, 2014 #8


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    Last edited: Jul 19, 2014
  10. Jul 19, 2014 #9

    jim hardy

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    aha !


    This figure from your link i grasp, from my old control system days..


    but how does one know in that continuous bitstream pouring out the right end which bit is the beginning of a reading?

    This could work, and in fact bears resemblance to successive approximation
    but they say n is just a few bits.
  11. Jul 19, 2014 #10


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    The easiest way to draw a diagram of how a S-D converter works is to show a relatively low oversampling rate, which leads to apparently high noise levels.

    In practice you can make the noise a small as you like with sufficiently high oversampling. The S-D converters used in audio applications (e.g. most consumer-level digital audio equipment) use oversampling factors like 4096x and sample rates of the order of 50 to 100 MHz, which gives S/N levels approaching 100 dB at audio frequencies.

    I've no idea how that relates to the OP's device - I couldn't find a nice summary of the spec anywhere in the mountain of documentation on the web site.
  12. Jul 19, 2014 #11

    jim hardy

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    page 370 here has an all-too-brief introduction, but presumes a level of familiarity beyond my own.

    my question is simpler - how does one construct a binary number out of that bitstream ?
    I can see that the closed loop will generate a real time series of one and zero bits
    but which nineteen of them do you choose for the number representing the analog value ?
  13. Jul 19, 2014 #12


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    That is the job of the low pass digital filter/decimation filter.

    Low pass digital filter:
    A fancy way to count the number and relative position of high bits during a interval of time (much longer than X bits of time in the bitstream) with a running average counter total that will be the ADC binary digital output of X resolution bits needed.

    Decimation: Just tossing out the redundant over-sample results in the binary digital output to reduce the output data rate for the much lower frequency filtered signal.
  14. Jul 20, 2014 #13


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    It's your lucky day. Analog Devices markets an isolated sigma-delta modulator (just the modulator without the decimation filter). It goes into some detail on how to implement the decimator and even includes sample Verilog code. This should answer all your questions.


    Typically sigma-deltas are not used in situations where you need a tight correspondence between a specific digital output and a specific input sample (because in principle the output code is by definition a combination of a large number of samples). For example, usually in a multiplexed system you would try to choose a SAR converter unless you had a good reason to use sigma-delta (for example a really high dynamic range requirement). It can be done but it's tricky. Sigma-deltas really excel in frequency domain applications or when you are making an essentially DC measurement so the timing spec is loose.

    I have over 250 million sigma-delta ADCs out in the wild. (I did the ADC for a very high volume part). Sigma-delta modulation is a truly beautiful idea. One of those ideas that seems like magic until you get your head around it.
  15. Jul 21, 2014 #14

    jim hardy

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    i'll say. What's amazing is not that it works, but that somebody thought of it.

    My first foray into Verilog. Still a bit of a puzzle, but the pieces are at last shown.
    Thanks to both you and nsaspook for those datasheets - i've saved copies.

    old jim
  16. Jul 21, 2014 #15
    I just did some tests on the device and recorded the ADC values and PPM outputs, it really shows the averaging effects talked about previously.

    Attached Files:

  17. Jul 21, 2014 #16


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    In case you're interested, Jim, here is an outstanding tutorial article about sigma-delta ADCs. It's incredibly well-written and easy to understand.


    Max worked on the first fully integrated CMOS sigma-delta ADC (although obviously he didn't invent the concept). In case you have access to IEEE Xplore or something here's the reference:

    Max W. Hauser, Paul J. Hurst, Robert W. Brodersen; MOS ADC-filter combination that does not require precision analog components, IEEE International Solid-State Circuits Conference, vol. XXVIII, pp. 80 - 81, February 1985.

  18. Jul 21, 2014 #17

    jim hardy

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    Thanks - i saved that one too.

    I'm hung on the decimator i think, doubtless due to my unfamiliarity with dsp basics. This one and the AD7401 should help a lot.

    The closed loop analog to bitstream i'm fine with, have used similar technique for analog multiply-divide functions in fluid flow metering.
    Somehow that bitstream gets anded with clocks and accumulated to produce a digital word that's orderly, ie progresses from msb to lsb . I'm still working through the verilog code in that AD appnote.... trying to grasp that ultra simple(to you guys) process of changing from a bitstream to an orderly word.. It has to be in the way those 23-wide integrator(accumulator?) and differentiator registers get filled?
    Probably some elementary DSP principle.....

    Anyhow thanks for investing the time in me. I'm still stumbling up the Verilog curve - it's enough different from Basic that i am very slow at it. Wiki has a Verilog article that's helped with things like the <= symbols that are so different in meaning from Basic. Flow seems different too; and array elements don't seem to be always subscripted?

    If i 'get it' this will be a milestone.

    old jim, plodding along as usual..
  19. Jul 21, 2014 #18


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    I think what's confusing you about Verilog is that it's a parallel language. The "<=" statements are what are called "non-blocking assignments" which means that all the "<=" statements in an always block are updated simultaneously, not sequentially like in a BASIC program. A great website to learn Verilog is:


    The decimator isn't all that simple so don't feel like it's intuitive. You could use a simple integator to recover the data (accumulator and integrator are synonyms). A first-order sigma-delta modulator is the simplest conceptually. If you had an oversampling ratio of 1024, for example, you would just average 1024 bits and the output of the digital averaging circuit (just the integrator you mentioned, it's that simple) would be orderly progressing from MSB to LSB. People do just this sometimes if you need a medium performance auxiliary ADC internal to an ASIC, for example.

    The decimator in the datasheet I posted is more complex that a simple integrator. It's a Sinc^3 integrator which is a DSP circuit.


    Why did Analog Devices put a sinc filter in their datasheet? The idea is that the transfer function of a simple first-order integrator (a digital integrator is the same thing as a digital first-order lowpass filter) isn't steep enough to filter out enough of the noise-shaped quantization noise. The reason people use Sinc^3 filters for second order-modulators is if you used a simple integrator you would end up leaving a bunch of potential performance on the table.
  20. Jul 21, 2014 #19


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    I thought of a simpler way to explain the decimation filter.

    If you were to put a simple RC lowpass filter at the bitstream output of the sigma-delta modulator you'd expect to see a voltage that was proportional to the ratio of 1s and 0s, correct? For example, if the modulator output is all ones, you'd get the voltage of a single one at the output, if you have an equal number of 1s and 0s you'd get a mid-scale voltage and so on.

    The digital integrator is doing just this, but in the digital domain. The output is simply the average number of 1's it has received since the last reset. That's all.

    The sinc^3 filter in the datasheet is more complex, of course, but in principle it is the same, just like a 4th-order butterworth filter is more complex than an RC lowpass filter, but they both work in essentially the same way.

    Is that helpful?
  21. Jul 21, 2014 #20

    jim hardy

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    obviously this gizmo is over my head.

    three-ish counts per microvolt?
    I'm amazed. Temperature change along your test leads can induce microvolts by the dozen.
    Our 14 bit A/D had a 2 millivolt range which is around i think 8 counts per microvolt
    but we being an industrial not a lab environment had a really hard time finding a microvolt standard to calibrate it. Fortunately we had no need of better than about ten microvolt accuracy, around a quarter degree on our thermocouples.
    I cannot imagine how you resolve let alone produce nanovolts.

    Point being - does observed 3 counts per microvolt mesh up with your expected resolution from your first post?
    I thought you expected one count per 76 microvolts.

    "One experiment is worth a thousand expert opinions...."

    old jim
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