ASIC Logic Gates NAND Homework: Solving 2-Input NAND Gate Circuit

[bradzyc]

Homework Statement

Hi everyone,

Very new to this forum so please bear with me!

I have an assignment as part of my engineering course that I seem to be struggling with so I'm wondering if I can grab some help.

Basically I have a water tank that feeds three separate processed (A, B, C). When any two of the processes are in operation at the same time, a signal is required to start a pump to maintain the head of water in the tank. I have to design a logic circuit using only NAND gates to meet the requirements. Then devise a logic circuit using only NOR and NOT gates.

Just a quick note also, the NAND gates can only be 2 Input NAND gates and not the 3 Input ones.

Homework Equations

Truth Table for all possible states and the required output
A B C P
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 1

The Attempt at a Solution

I was not present during this lesson due to work requirements so I'm wondering, how would I go about doing this because at the moment, I'm just using trial and error and having to constantly redraw the circuit out and test different activated processed (i.e. A=1, B=0, C=1) until I seem to get the right answer. However, I have not got this yet.If anyone could point me in the right direction or help then it would be much appreciated.

Cheers People!
B

 

[jedishrfu]

Can you design it using AND and OR gates and then replace them with NAND gate equivalents?

 

[NascentOxygen]

You can convert your truth table into Boolean algebra by looking at the lines where P is true:

P = B.C + A.C + ... (you can complete this line)

Next, can you simplify this line?

 

[bradzyc]

You can convert your truth table into Boolean algebra by looking at the lines where P is true:

P = B.C + A.C + ... (you can complete this line)

Next, can you simplify this line?

Hi.

Yes I already have P=B.C + A.C + A.B

Isn't this the simplest it can be whilst conforming to De Morgan's laws?

 

[bradzyc]

Can you design it using AND and OR gates and then replace them with NAND gate equivalents?

Hi,

I have already designed it with AND and OR gates however I can't understand how to convert this to NAND

 

[jedishrfu]

There are known conversions for a two input AND gate, a two input OR gate and an INVERTER gate:

http://en.wikipedia.org/wiki/NAND_logic

and similarly for NOR logic:

http://en.wikipedia.org/wiki/NOR_logic

 

[bradzyc]

Sorry guys just been told that we can use a 3 input NAND and solved it.

C and B connected to NAND 1
C and A connected to NAND 2
B and A connected to NAND 3

Then all 3 NAND's connecting to a final NAND

Many thanks for all your help!
B

 

[Merlin3189]

So, just for fun, why not complete it with just 2ip NANDs !
Takes me 7 NANDs (and maybe 2 minutes), but I don't use any DeMorgan or Boolean algebra, so there may well be shorter ways.

 

[bradzyc]

So, just for fun, why not complete it with just 2ip NANDs !
Takes me 7 NANDs (and maybe 2 minutes), but I don't use any DeMorgan or Boolean algebra, so there may well be shorter ways.

Why not! Could you show me your solution? I'm really not getting it!

 

[Merlin3189]

Ok. Of course, when I typed it up, I found an error and now it is 8 gates!

I've done a drawing and also an Excel spreadsheet which I think may be helpful.
Drawing is attached. I can't attach the Excel (AFAIK), but I've attached a screenshot.

My thinking was, the first level of nands will be low if both inputs are true, so I need any of the outputs to be low.

Second layer, if all inputs are high, output will be low, so I need either of them to output high, showing an input was low.

Now is where I made my error and had to correct it by inverting these outputs.
If I invert them, then I need either inverted output to be low.

The final nand is high unless both its inputs are high, so it is high if either input is low.

I know that is probably confusing! It's hard to explain my thinking process.
1 - I just believed it must be possible
2 - 3 inputs mean 3 pairs so 3 nands. That gives me signals showing a pair of 1's
3 - I've got to get it down to 2, so try combining with just 2 nands and see what I get
4 - Now I've got a 1 if any of the pairs was good.
5 - Nand is no use to spot a single 1, so invert them to spot a single 0
6 - Final nand is high if either input is 0.

Final bit of info. I tried to do an LTspice circuit of this, but could not manage that(!), so I went to my old friend Excel. The screen I show is the result. AB&C are the inputs, E,F&G are the first level Nands and so on.
So the formula in column E is =Not(And(Ax,Bx)) using Not(And) because there is no Nand.
Column I is =Not(And(Ex,Fx))
Column L is = Not(And(Ix,Ix)) just to show I'm not cheating! I could have simply put = Not(Ix)
And final column O is =Not(And(Lx,Mx))

I have highlighted the rows which should give a True (1) output.

No doubt the methods taught in your course are better and I do use some of them sometimes. But I really like to see what is going on, if I can. The comment someone made about using LTspice is probably very good advice. Make up circuits in whatever modelling system you can (even Excel!) and play around.