For the ALS logic circuit, estimate:
(a) the current IOL
(b) the delay in a 1-to-0 transition at one of the inputs of GATE 1
appearing as an effect at the output of GATE 5.
(c) the total power consumed by the circuit in a quiescent state.
The Attempt at a Solution
I think this a NAND gate logic circuit, in red I have added the inputs and outputs. I have cropped part of a table, that showed typical values of certain logic families, to show the spec of an ALS. I think I am right in saying that this can only be an 74ALS. For (a) the low level output according to the table is 4mA, The low level inputs for gates 2,3 and 4 are 100uA each.
I don't know how or where to find the formulas to solve and my notes are dire.