Bad Circuits - Test Your Knowledge

[berkeman]

The only distinction between the straight 1 ohm resistor, I exampled, and the zener setup is that in the zener case the 1 ohm resistor is the sum of r_bias + R_z.
Also V_ref occurs at the junction of R_bias and R_z.

I don't see what is so difficult with this concept
And yes, it works this way in practice.

I'd like to take this offline via PM with NoTime for a bit, to see if I can better understand what he is saying. We'll report back with a resolution in the next couple days, I would guess. That will keep this thread going on the new problems more cleanly.

Thanks.

 

[ranger]

For circuit F [Zero-Crossing Counter], I'm asking myself - what if the input signal is noisy? We surely won't want false triggering of the counters when the input signal [nosily] oscillates about its zero crossing position. The way the circuit is now, its just a plain old comparator; a perfect candidate to swing its output as a function of the noise that may be present on the input signal on the non-inverting input. We need to give the circuit a good degree of noise immunity. For this I suggest that we use positive feedback to give the circuit hysteresis. We would effectively be building a schmitt trigger around the 741 by doing this.

I'll see if I can find more stuff wrong with F tomorrow.

 

[ranger]

Hey berkeman, is it too early to sum up the problems we were having with the current source op-amps?

 

[berkeman]

Hey berkeman, is it too early to sum up the problems we were having with the current source op-amps?

Not at all. Would you do that for us please? (You understand them, I'm pretty sure.) Please leave out the Zener power dissipation issues right now, though. NoTime and I are using SPICE simulations to resolve the disagreements via PMs.

BTW, I don't know if this came out in the Zener discussions or not, but 5.1V Zeners have the tempco closest to zero. So if you need to use a Zener for a voltage reference and want a good tempco, use a 5.1V Zener (biased at its specified Iz) and multiply it up or down if you need a different voltage.

 

[berkeman]

For circuit F [Zero-Crossing Counter], I'm asking myself - what if the input signal is noisy? We surely won't want false triggering of the counters when the input signal [nosily] oscillates about its zero crossing position. The way the circuit is now, its just a plain old comparator; a perfect candidate to swing its output as a function of the noise that may be present on the input signal on the non-inverting input. We need to give the circuit a good degree of noise immunity. For this I suggest that we use positive feedback to give the circuit hysteresis. We would effectively be building a schmitt trigger around the 741 by doing this.

I'll see if I can find more stuff wrong with F tomorrow.

That's definitely part of the problem. But even if there is no noise in the input signal, a comparator almost always will need some form of hysteresis (via attenuated positive feedback) around it. What you commonly run into, is that the act of the comparator or opamp switching its output generates enough of a transient in the chip's internal power supplies and internal circuitry to make apparent differential noise at the inputs. So even if you have a perfectly clean signal and great PCB layout and decoupling, the switchover point of a comparator without hysteresis will have multiple buzzing transitions. If you ever see a comparator shown in a circuit without hysteresis, that is a red flag to look further.

That having been said, in the last work project that I helped out with, we used comparators with zero hysteresis in the reciever of a network transceiver. I have to be a little careful what I say about this, but as a Quiz Question -- When do you think you could use a comparator with zero hysteresis when receiving an analog signal with the goal of accurately digitizing its zero crossings?


(EDIT -- clarified a bit about the output --> internal noise feedback issue)

 

[AlephZero]

More problems with the zero-crossing counter:

There are two power supply options shown, and each has a problem.

1. With the +15/-15 supply, the input to the 7493 will flip between about +13/-13V. Since the 7493 is a TTL device with 5V upply, this is not a good idea. The absolute max voltage for TTL inputs is usually +5.5V or +7V.

2. With the +5/0 supply, the comparator won't work at all because one op-amp input is grounded. The output from the opamp will probably be stuck close to +5V.

3. To drive TTL from an opamp with a +5/0 supply, you need an opamp where the output can swing right to to supply levels. The TTL logic levels are < 0.8V and > 2.0V. A 741 isn't the right part to use for this. You need an opamp that is designed to work on a 5V supply and the output can swing rail-to-rail.

 

[ranger]

That's definitely part of the problem. But even if there is no noise in the input signal, a comparator almost always will need some form of hysteresis (via attenuated positive feedback) around it. What you commonly run into, is that the act of the comparator or opamp switching its output generates enough of a transient in the chip's internal power supplies and internal circuitry to make apparent differential noise at the inputs. So even if you have a perfectly clean signal and great PCB layout and decoupling, the switchover point of a comparator without hysteresis will have multiple buzzing transitions. If you ever see a comparator shown in a circuit without hysteresis, that is a red flag to look further.

Another little circuit design tip that I have to put in (as H&H calls it) bag of tricks.

That having been said, in the last work project that I helped out with, we used comparators with zero hysteresis in the reciever of a network transceiver. I have to be a little careful what I say about this, but as a Quiz Question -- When do you think you could use a comparator with zero hysteresis when receiving an analog signal with the goal of accurately digitizing its zero crossings?

At first I can see no need for this (my lack of experience), but the more I think about it, there may be use after all. There has to be some transmission protocol out there that has a specification where it requires a very small input differential to be detected and pass as valid data. If we add hysteresis to our comparator, there is a chance that we may lose some data.

 

[ranger]

Voltage-controlled current source and 200mA "current source" - solutions

Wrapping up the possible problems with the circuits in post #74; circuits D and F.

Circuit D - Voltage-controlled current source
*The solution for this one is pretty simple. We need to swap the positions of the resistor and the load. D won't work because the opamp is supposed to be operating in a linear mode, but its two inputs are different voltages^[1]. With the circuit we'd want to fix it by having R connected to the inverting input to ground. And have the load connected to R and the output of the op-amp.

Circuit F - 200mA "current source"
*Pushing 200mA of current through the zener may be a bad idea. The original configuration of circuit F does just this. As a fix for this problem, we could use the topology in the fixed circuit D. It would be best to have the zener be used as a voltage reference (to the non-inverting input) and have the load hooked up to the inverting input - circuit F fixed. This fixed version uses negative feedback, meaning that we would have the zener reference voltage at the inverting input - remember one of the golden rules of op-amps as outlined in the Art of Electronics - the op-amp's output will attempt to do what it can to bring the voltage differential between the two inputs to zero (provided we use negative feedback; see chapter 4 for more discussion on this). So if we use R to be 45ohms, we'd have a current of 200mA thru the load. IN this configuration we don't have to worry about excess current thru the zener because we are using the resistor to get the appropriate zener current for voltage regulation.

*Even with the fix mentioned above, we still have problems because we are dealing with real op-amps here i.e. non-ideal. 200mA is a lot of output current to ask from a general purpose op-amp.

*Next we have the issue of unbalanced input impedances. Remember that we have input bias current. Due to unmatched impedances on both op-amp inputs, we'll have some error introduced. In addition to matching the impedances, we could use an op-amp with very little input bias current (BJT input stage) or very little leakage current (FET input stage).

 

[sheldonstv]

whats wrong with this circuit?

 

[berkeman]

At first I can see no need for this (my lack of experience), but the more I think about it, there may be use after all. There has to be some transmission protocol out there that has a specification where it requires a very small input differential to be detected and pass as valid data. If we add hysteresis to our comparator, there is a chance that we may lose some data.

For the data detection in the network that I have in mind, it is important to detect the zero crossings, without any delay or offset that hysteresis would generate. The buzzing that can happen at the zero crossing detection by comparators without hysteresis is actually removed by subsequent digital signal processing in this case. The buzzing is at a much higher frequency than the data rate, so it's relatively easy to filter out with DSP. In a circuit like the Bad Circuit edge counter, extra edges of any frequency will give an incorrect answer.

 

[berkeman]

More problems with the zero-crossing counter:

There are two power supply options shown, and each has a problem.

1. With the +15/-15 supply, the input to the 7493 will flip between about +13/-13V. Since the 7493 is a TTL device with 5V upply, this is not a good idea. The absolute max voltage for TTL inputs is usually +5.5V or +7V.

2. With the +5/0 supply, the comparator won't work at all because one op-amp input is grounded. The output from the opamp will probably be stuck close to +5V.

3. To drive TTL from an opamp with a +5/0 supply, you need an opamp where the output can swing right to to supply levels. The TTL logic levels are < 0.8V and > 2.0V. A 741 isn't the right part to use for this. You need an opamp that is designed to work on a 5V supply and the output can swing rail-to-rail.

Good stuff, AlephZero. There's at least one more thing that is generally wrong with the circuit, having to do with the counters. Any ideas?

 

[berkeman]

whats wrong with this circuit?

I'm not very good with 555 circuits... Where is this one from?

 

[sheldonstv]

its one of my own design with a deliberate mistake on the schematic-not too hard to spot if you have a close look...

 

[ranger]

For circuit F [Zero-Crossing Counter]:

*Should we not use a comparator chip like the 311? We could build hysteresis around the 311. I'm suggesting this because of the limited slew rates of general purpose op-amps.*Would it also be a good idea to use a pair of input protection diodes on the input of the op-amp [thats getting the analog signal]? Just being careful that we don't exceed the maximum voltage differential allowable by the 741. But then again if we're dealing with relatively small signals there's no need for this.

 

[ranger]

Circuit G - SR Latch

It would be a idea to have both inputs grounded when we want to send in a LOW signal. Unconnected pins are usually a bad idea. If we are dealing with TTL inputs, an unconnected input is about 1.3V, but there is no current. Also there is no noise immunity in this case.
If we were using CMOS, we should also have the inputs grounded when we need a LOW.

 

[sheldonstv]

nobody know?re 555 circuit?

 

[dlgoff]

"nobody know?re 555 circuit?"

okay. It's hard to tell from you skematic but it looks like you have the output connected to the threshold and the discharge.

 

[sheldonstv]

that is one fault yes...there is one more if you have a careful look...

 

[berkeman]

that is one fault yes...there is one more if you have a careful look...

One thing that would help on your Bad Circuit post, would be if you could give a web pointer to the best web page for info/tutorial help on the 555 IC. I've played with them way back in school, but never really liked them much. But there are a fair number of posts here on the PF about 555 questions (mainly from students having to use them in labs), so a good web tutorial about them would be helpful. There is the datasheet that I could go find and read through, but it would be better if there were something like a "Circuit Ideas" web page for the 555 timer/monostable IC. Anybody have a good pointer? Thanks much!

 

[ranger]

Hey berkeman, no comments on the previous circuits you posted (post #134 and #135)?

 

[berkeman]

Hey berkeman, no comments on the previous circuits you posted (post #134 and #135)?

Sorry, I got buried at work for a bit. Yes, you have identified most of the bad things with [F] and [G] in my post #117.

[F] There needs to be hysteresis in the comparator part of the circuit (the LM741 opamp), and the output voltage levels need to be fixed to be TTL compatible. You make a good point that some signal conditioning of the input signal and clamping of the signal before the opamp would be a good idea, depending on the characteristics of the signal source. There are several ways to fix the output drive -- I'd probably go through an output PNP pullup stage to adjust the bipolar comparator output to TTL/CMOS levels. The other issue that I was looking for with the digital counter stages is that they are ripple counters (and worse yet, two in series), so the "output" number is not going to be valid after an input clock until all of the stages settle out. The "output" will be garbage during the rippling transitions, so whatever circuit this was being fed to would have to be carefully designed to accommodate this. A more real-world design would synchronize the output of the zero-crossing detector, and then use that synchronous signal to clock counters. The counters could be ripple counters, as long as they settle out in less than the internal clock period.

[G] Yeah, this is a dorked up version of the usual RS latch. The floating inputs are a mistake, and having two switches is a mistake, because what do the gates do if both buttons are pushed at the same time? The more traditional way to make a NOR latch is to pull both inputs to ground, and have a single-pole, multiple throw switch that can either pull up one input or the other. The switch needs to be a break-before-make type.

I have some pesky work stuff to take care of today, but I'll try to find something good to post tomorrow, maybe on synchronizing signals. In the mean time, it would be good to finish off the 555 circuit, if you folks have the time.

 

[ranger]

[G] Yeah, this is a dorked up version of the usual RS latch. The floating inputs are a mistake, and having two switches is a mistake, because what do the gates do if both buttons are pushed at the same time? The more traditional way to make a NOR latch is to pull both inputs to ground, and have a single-pole, multiple throw switch that can either pull up one input or the other. The switch needs to be a break-before-make type.

I have some pesky work stuff to take care of today, but I'll try to find something good to post tomorrow, maybe on synchronizing signals. In the mean time, it would be good to finish off the 555 circuit, if you folks have the time.

We will have a race condition when both of the inputs are activated simultaneously. This is basically saying that we cannot predict what the output would be.

I have another question, though not totally related to these circuits. If we take a TTL chip that has a totem pole (push-pull) output stage, why is it that it sinks current better than it sources? I assume by sourcing they mean when the output is HIGH and sinking is when the output is LOW? It still puzzles me, because if I look at the push-pull output stage, one transistor would be on at any given time (just ignore that very brief period when both are conducting and there is a path from +5V to gnd). When the output is HIGH, the transistor that is connected to 5V is conducting and when LOW the transistor that is connected to ground is conducting. I don't understand why the transistor connected connected to +5V cannot "source" current when compared to the one that is connected to ground.

 

[berkeman]

We will have a race condition when both of the inputs are activated simultaneously. This is basically saying that we cannot predict what the output would be.

Correct.

I have another question, though not totally related to these circuits. If we take a TTL chip that has a totem pole (push-pull) output stage, why is it that it sinks current better than it sources?

That's a good question, and probably better answered by someone else. But as I remember, the early TTL gates only used NPN transistors for some IC fabrication reason, so that makes the output drive asymmetric. The output stage is optimized for low quiescent current and clean output transitions, not for symmetry or pull-up strength. Contrast this circuit:

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/nand2.html

with the symmetric output stages shown in H&H in the section on "Push-pull output stages" (section 2.14 of the 1st edition).

With CMOS, they've used both n-channel and p-channel devices, and they generally size the p-channel (pullup) devices larger since they are weaker than the n-channel devices, so that you get symmetric drive.

 

[dlgoff]

"If we take a TTL chip that has a totem pole (push-pull) output stage, why is it that it sinks current better than it sources?"

Wouldn't it be because there's a collector resistor for the source transistor (push); causeing this asymmetric condition?

 

[berkeman]

Wouldn't it be because there's a collector resistor for the source transistor (push); causeing this asymmetric condition?

That would appear to be part of the problem as well. To fix it all, it looks like you would need to get rid of the phase splitter stage and add a PNP as the pullup stage (plus throw some other stuff in). Kind of like CMOS circuits, where the p-channel pullup and n-channel pulldown are driven with in-phase signals.

http://www.cs.umass.edu/~weems/CmpSci635A/Lecture2/L2.16.html


EDIT -- fixed broken link

.

 

[NoTime]

that is one fault yes...there is one more if you have a careful look...

Did you mean that as a fault?
In general, node marks don't seem to be all that consistently used for "T" connections, but if present then one is required for crossing lines to be connected.

Inever did much with 555s, but I only see one error that has to do with the potentiometer.
This could be corrected in the component callout.
They do make pots with stops and it has been my experience that they are not always marke as such on schematics.

 

[ranger]

That would appear to be part of the problem as well. To fix it all, it looks like you would need to get rid of the phase splitter stage and add a PNP as the pullup stage (plus throw some other stuff in). Kind of like CMOS circuits, where the p-channel pullup and n-channel pulldown are driven with in-phase signals.

www.cs.umass.edu/.../Lecture2/L2.16.html.

Berkeman, I'm getting a 404 on that link.

I've dispatched the question to one professors and I'm awaiting his response.

But I still have a question on the output stage: Let's assme the pull-up transistor is not conducting and the pull-down transistor is conducting. So since there is no path to +5V (pull-up transistor not conducting), what is the state of the collector on the pull-down transistor?
To get a visual of what I'm referring to, see H&H second edition, chapter 8; section 8.09 (IC gate circuits); Fig 8.17 (LS TTL NAND Gate).

Sorry for sidetracking this thread, I have no idea why this is suddenly bothering me. I guess its the entire source and sink thing.

 

[dlgoff]

"...what is the state of the collector on the pull-down transistor?"

Well the sink current is getting it's potential from some where (maybe the +5V). So there should be a potential on the collector depending on the load resistance of the source. If the transister is saturated, wouldn't the potential be ~0.2V?

 

[berkeman]

Berkeman, I'm getting a 404 on that link.

I've dispatched the question to one professors and I'm awaiting his response.

But I still have a question on the output stage: Let's assme the pull-up transistor is not conducting and the pull-down transistor is conducting. So since there is no path to +5V (pull-up transistor not conducting), what is the state of the collector on the pull-down transistor?
To get a visual of what I'm referring to, see H&H second edition, chapter 8; section 8.09 (IC gate circuits); Fig 8.17 (LS TTL NAND Gate).

Sorry for sidetracking this thread, I have no idea why this is suddenly bothering me. I guess its the entire source and sink thing.

Sorry about the broken link -- I used google images to find one, and didn't copy the link correctly. I think I've fixed it in my post, and here it is:

http://www.cs.umass.edu/~weems/CmpSci635A/Lecture2/L2.16.html

On your question about the pull-down transistor, dlgoff has it right. The bottom transistor will be close to saturated, and the pull-down current is just whatever the external load (the next gate's input or whatever) is supplying at that low voltage.

 

[ranger]

Ah yes, it sort of makes sense now. However (to quote dlgoff) "sink current is getting it's potential from somewhere (maybe the +5V)". It seems that it is hinted that the top of the collector (for pull-down transistor) is connected to +5V. But remember that the pull-up transistor is not conducting, so where is the pull-down transistor getting its +5V from in order to go into saturation? From the potential of the external load?