# Calculating Decoupling Capacitor When Datasheets Don't Specify Parameters

1. Nov 27, 2010

### ¡MR.AWESOME!

To calculate the value for a decoupling capacitor (Vdd pin to Vss), I use the formula
$$I=\frac{C \cdot dv}{dt}$$
But what do I do if I don't know the load capacitance?

For example, I have a push/pull comparator whose output is connected directly to an input of a PIC mcu. The capacitance of the input pin is not specified in the PIC's datasheet. I can't accurately calculate the decoupling cap value for the comparator's Vdd pin. What am I supposed to do? Is there another way to go about calculating it with different parameters? I just used missing capacitance as an example but what would I do if the rise time or some other parameter wasn't specified?

Relevant datasheets:
Comparator
MCU

On another note, what do you do when a datasheet gives a recommended value (0.1uF) for a decoupling cap, but if you actually do the math, you get a way different result? Should you stick with the recommendation even though it's likely that the writer just specified a rule-of-thumb value? Like on page 70 of this digital pot

2. Nov 28, 2010

### MATLABdude

As it was explained to me, you sometimes see sets of three decoupling capacitors in parallel with Vdd/Vss of ICs--1, 0.1, 0.01 uF (to handle transients of different frequencies).

The steady state behaviour of these is whatever the parallel capacitance happens to be. However, given that decoupling capacitors work on transient signals (keeping voltage up in event of brown out, or some degree of suppression of voltage spikes), you can consider these to work more or less independently of each other. For the most part as long as they can supply current to the IC, and smooth out the supply voltage, they'll work reasonably well in their assigned role.

I'd adopt a more experimental approach: does the rule of thumb work? If so, great! If not, try what the calculations give you. If neither of these approaches work, figure out where you're getting voltage spikes (e.g. with motors or coils) or noise and try to suppress these (with flyback diodes, or through isolation of grounds or the likes).

3. Nov 28, 2010

### Studiot

Decoupling capacitor values are not super critical. That is why there is a predominance of
1.0 x 10-something F capacitors used.

The important factor is that the impedance of the decoupling cap is low compared with the impedance of the circuit it is decoupling - at the frequency concerned.

Yes the larger the capacitance the poorer the HF response (for cheap caps anyway and decoupling caps are the cheap ones) so sometimes wideband decoupling is performed by several caps in aprallel.

4. Nov 28, 2010

### ¡MR.AWESOME!

Thanks for the replies guys.

I like that. It's nice and simple. Is that usually how it's done in a professional setting?

5. Nov 28, 2010

### Staff: Mentor

For SMT digital ICs, I will usually put one 0.1uF decoupling cap per rail input to the IC, and place the cap on the same side of the PCB as the SMT IC, with the rail side of the cap as close as possible to the IC rail input pin. Via the ground side of the cap to the voltage plane as close as possible to the rail side SMT pad of the cap. All of this helps to minimize the inductance of the decoupling cap, which is really important for RF decoupling quality.