Can you please tell me the name of this component?

[Guidestone]

Hey guys, I don't know if this question is supposed to be in the homework questions section, If it is then I'm sorry. I just want to know the name of this component (the one inside the red box). It looks like a flip flop, I'm not sure. I just haven't been able to find it on the internet and I have to know what it is and what it does in the circuit for homework.
Thank you tons!

 

[jedishrfu]

My guess is its a D latch.

What do you think the circuit does?

 

[Guidestone]

It is the output A4 of the pic16f84 microcontroller. It's supposed to let data out whenever there is a 1 in the WR Tris flip flop output and it is supposed to let data in whenever there is 0 in the WR Tris flip flop output. If it let's data in, then the signal gets filtered by the buffer and it goes to D. I guess D is the same as Q but the data in D can only change whenever there's either a 0 or 1 at the RD port. 1 at the RD port and at Q should result in a 1 at the data bus. I think my unknown component just transfers data when there's something at RD, I don't know what it exactly is though.
I already searched the D latch and it got really close but what I found had a fourth letter in the lower left corner.
Thanks anyway :)
Please, if anyone finds the component familiar, let me know.

 

[jedishrfu]

You could check this out:

https://courses.cs.washington.edu/courses/cse370/08wi/pdfs/lectures/14-Flip-flops.pdf

They use similar notation.

 

[Jeff Rosenbury]

I find the component familiar. It is a D type flip flop. However the data is flowing backward which can throw one off. The data bit (D) enters from the right instead of the more normally depicted left. The output (Q, for quiescent) is on the left where inputs normally go. I'm sure this was done to make the wires look better.

The enable input (EN) on these is often edge triggered, but this one isn't. (At least according to this schematic. I might consider a missing edge trigger symbol if the logic doesn't work out quite right. Check the BOM (Bill of Materials) if that's the case. I've found mistakes on occasion.)

So when the enable is high, the data flows through to the output. When it goes low, whatever is on the data line at that point is latched in the flip flop until it goes high again. (Or it latches on the edge trigger if the schematic is mistaken.)

 

[meBigGuy]

It is generally called a transparent latch. EN high makes it transparent. EN low, it holds the last output value.

 

[Guidestone]

Thanks a lot guys. I could finish my homework succesfully. Jedishrfu your pdf was really useful. meBigGuy, what you said made a lot of sense when I analised the circuit again.
:)

 

[CWatters]

The signal RD Port is connected to the enable of the D Type latch via an inverter. This prevents the input data changing when the input port is being read. This helps if the inputs are asynchronous.