Designing a 150MHz Clapp Oscillator with 0.24u Inductance for Your Project

[AHMEDbr]

hi , i want to design a clapp oscillator with output frequency up to 150 MHZ , inductance value must be 0.24 u , who can help me please?? i need it for my project

 

[anorlunda]

https://en.m.wikipedia.org/wiki/Clapp_oscillator

Especially the references linked at the bottom of the article.

 

[AHMEDbr]

https://en.m.wikipedia.org/wiki/Clapp_oscillator

Especially the references linked at the bottom of the article.

i saw the references but i don't have any solutions

hi , i want to design a clapp oscillator with output frequency up to 150 MHZ , inductance value must be 0.24 u , who can help me please ?? i need it for my project

 

[AHMEDbr]

here is my oscillator design , the output frequency must be 150 MHZ but the simulation in ltspice is 147 MHZ

 

[anorlunda]

Tagging @berkeman

 

[davenn]

here is my oscillator design , the output frequency must be 150 MHZ but the simulation in ltspice is 147 MHZ

I don't know why you must keep the value of the inductor what it is ??

have you considered experimenting with the values of C1 and C2 C1=C2 but change the values to 33pF instead of your 50pF
as according to the freq formula for a Clapp Osc, they will also help set the frequency

you just haven't done enough experimentingDave

 

[AHMEDbr]

i'm working in model , so that the inductor value must be kept at 0.24 uH , the VCC must be 3.3 V , and i must use a JFET , the output frequency must be 150 MHZ , can you help me with others design ?

 

[davenn]

i'm working in model , so that the inductor value must be kept at 0.24 uH , the VCC must be 3.3 V , and i must use a JFET , the output frequency must be 150 MHZ , can you help me with others design ?

I really don't see the reason for all those musts, except for maybe the voltage

I have given you an option go try it in your simulator and experiment with the values of C1 and C2
come back with your resultsDave

 

[AHMEDbr]

i tried your option but i found 144 MHZ

 

[davenn]

i tried your option but i found 144 MHZ

sooo ... did you think of trying other values ??
start thinking about the problem
so if you went to 33p and the freq dropped, what do you think that is telling you ?
what should you try next ?

 

[AHMEDbr]

really i don't know , i tried many values but always the same problem

 

[davenn]

really i don't know , i tried many values but always the same problem

come on ... seriously ??

so if the 33p dropped the freq ... how about something higher than 50p ... say 60p or 75p
see what that does

 

[davenn]

I want you to find a pair of values that will take you a little above 150 MHz
THEN you can change out C3 for a trimmer cap with a centre value of ~ 10p
and use that to adjust to your wanted frequencyDave

 

[AHMEDbr]

I Tried with c1=c2 = 50 pF and C3 = 5.5 pF i found 150 MHZ :) but when i calculated i found 153 MHZ !

 

[Baluncore]

AHMEDbr.
The LTspice circuit shown in post #4 has D1 as a bias or limiter component, but D1 is the wrong way round to DC bias an N-JFET.

In post #9 the diode has gone, but there is still no gate DC bias.
You need to DC bias the gate by replacing D1 with a 47k resistor between ground and JFET gate.

 

[berkeman]

Thread closed for Moderation...

EDIT -- Thread re-opened after being moved to the Homework Help forums. Reminder to all to please use the Report link to let the Mentors know about newbies misplacing schoolwork questions in the technical forums. Especially with so little effort shown initially. Thank you.

 

[berkeman]

I Tried with c1=c2 = 50 pF and C3 = 5.5 pF i found 150 MHZ :) but when i calculated i found 153 MHZ !

Have you actually looked at the equations for the frequency of oscillation of this design? What is the exact homework problem statement? With a circuit like you show in your simulation schematic, the oscillation frequency will vary a lot with temperature and component tolerance. If you need that exact oscillation frequency, you will need to do a lot more than what is shown in your schematic...

 

[davenn]

Have you actually looked at the equations for the frequency of oscillation of this design?

I had asked/commented about that way back in post #6

 

[davenn]

I Tried with c1=c2 = 50 pF and C3 = 5.5 pF i found 150 MHZ :) but when i calculated i found 153 MHZ !

so apart from the missing bias resistor, baluncore pointed out. What other things do you think would
cause a difference between what freq you got in the sim and the freq you got for an actual circuit ?

 

[AHMEDbr]

hi everybody , i replaced the diode with a bias resistor as Baluncore said , but i found 147 MHZ , should i add a temperature compensation to my circuit ?

 

[davenn]

should i add a temperature compensation to my circuit ?

do you see the frequency changing with temperature ?you haven't tried my other suggestions yet

 

[AHMEDbr]

i Tried with c1=c2= 33p and c3 = 6pf , i find 150 Mhz with a bias resistor of 47k :) thank you all :)

 

[Baluncore]

You are only specifying capacitors to two digits, while the real ones will probably have a 5% tolerance, so why do you worry about a 2% difference between the crudely predicted frequency and the LTspice simulated frequency. Once you build a VHF circuit on a PCB it will change again and you will need to trim the frequency with a variable capacitor. It is a mistake to fine tune a simulation beyond what is sensible.

When measuring time and frequency, do not use the poorly defined flat part at the top of a sine wave, use two cursors and place them at the same voltage on the steepest part of the wave form. That will be much more accurate.

Select the plot window then 'view' FFT, to get a better estimate of frequency and see the harmonic distortion of the oscillator.
Change the FFT frequency axis to linear and use dB for the vertical axis.

Rather than fine tuning frequency, play with the model to find the extreme component values that will still oscillate reliably.
You can then manufacture a very reliable product by using values that lead to stability.

You might try changing the source resistor to change the JFET operating point, which should reduce power consumption and maybe change the output voltage range relative to zero.

You might try changing the 33pF capacitors and 47k bias resistor to get a faster more reliable start-up of oscillation.

LTspice has a temperature step command so you can check semiconductor temperature variations.
Paste the command .Step Temp 0 40 10 onto your circuit schematic using the .command text button on the RHS of the toolbar.

It is normal practice to build real circuits by selecting capacitor types that cancel the thermal changes of the inductors.

 

[gneill]

A couple of things to note:

1) Clapp oscillators often place a trimming capacitor in series with the inductor for calibrating the frequency.

2) While most simple AC models for FETs depict the gate as an open circuit, this assumption can bite you at higher frequencies. Check the datasheet for your FET for any capacitances they list. (You can also look at the LTSpice component entry and look at its parameters).

 

[davenn]

1) Clapp oscillators often place a trimming capacitor in series with the inductor for calibrating the frequency.

yes, I had noted that earlier as a choice for fine adjustment of frequency

2) While most simple AC models for FETs depict the gate as an open circuit, this assumption can bite you at higher frequencies. Check the datasheet for your FET for any capacitances they list. (You can also look at the LTSpice component entry and look at its parameters).

yup, worthwhile considerations Dave

 

[AHMEDbr]

Thank you for all your advices :)