CMOS NAND Circuits Draw Current? Lab Notes Explained

[mmmboh]

In my lab notes, it says that the connection of CMOS NAND circuits will draw non-negligible current...but I thought the point of the CMOS was because it uses such little current, at least that's what I wrote in my notes..I don't get it, what's going on?

 

[╔(σ_σ)╝]

Yes, the CMOS implementation draws little current. Your lab notes are wrong ?!

 

[mmmboh]

I don't think they are wrong as it says so explicitly, and it's done in a way that acknowledges that this is unusual..this is the circuit if it makes a difference [PLAIN]http://img10.imageshack.us/img10/8317/lab7w.jpg.

I just don't get this "contradiction".

 

[skeptic2]

What do your lab notes consider non-negligible current? Here's a link to a data sheet for a cmos nand gate that draws a maximum of 1 uA under all conditions and 100 nA at 18 V and 25 C. Is that negligible?

http://pdf1.alldatasheet.com/datasheet-pdf/view/66402/INTERSIL/CD4023.html

 

[mmmboh]

Hm, I'm not sure what they consider non-negligible, it just says non-negligible...I guess any more current than it theoretically should. I don't know the explanation for this non-negligible current though, it shows us how the CMOS NAND is built and tells us the reason has to do with that, but I don't know the explanation.

 

[chroot]

Hey mmmboh,

The idea is that CMOS circuits use virtually no current when they're in steady-state. If you have some network of NANDs and all of the inputs are constant, not changing in time, then the CMOS circuit uses very little current. The only current it uses is called "leakage," and it's negligible in most situations. When the inputs change, though, the gate capacitance of the transistors has to be charged or discharged, and that does consume current.

The circuit they gave you is kind of a trick. They're driving the input of the NAND gates to mid-scale, halfway between the two supplies. This is a no man's land, somewhere between logic-0 and logic-1. This voltage is adequate to partially turn on both the NMOS and PMOS devices in the gates, so a continuous (and possibly large) current will flow.

Normally, when a CMOS gate changes state, its output changes so rapidly that the voltages are only in the no man's land for a short time. Except during these brief transitions, the voltage is stable, very close to either supply. Because the transitions are so rapid, the total power loss is very small.

- Warren